Equivalent construct in VHDL

[Ved]

Hi
I need a faster sort algorithm, which I got at
http://www.engr.sjsu.edu/crabill/ in lecture module5.

I am an ardent VHDL user. So I need to convert the verilog code to
VHDL.
I am attaching the code for convenience.

Is there any VERILOG to VHDL converter available?
I could find VHDL to verilog converter in abundance but no verilog to
vhdl.
--------------------------------------------------------------------------------------------


`timescale 1 ns / 1 ps

module oetsort(clk, in1, in2, in3, in4, in5,
out1, out2, out3, out4, out5);
input clk;
input [15:0] in1, in2, in3, in4, in5;
output [15:0] out1, out2, out3, out4, out5;

reg [15:0] dat1s0, dat2s0, dat3s0, dat4s0, dat5s0;
reg [15:0] dat1s1, dat2s1, dat3s1, dat4s1, dat5s1;
reg [15:0] dat1s2, dat2s2, dat3s2, dat4s2, dat5s2;
reg [15:0] dat1s3, dat2s3, dat3s3, dat4s3, dat5s3;
reg [15:0] dat1s4, dat2s4, dat3s4, dat4s4, dat5s4;
reg [15:0] dat1s5, dat2s5, dat3s5, dat4s5, dat5s5;

always @(posedge clk)
begin
// This implements the input registers.
dat1s0 <= in1;
dat2s0 <= in2;
dat3s0 <= in3;
dat4s0 <= in4;
dat5s0 <= in5;

// This implements the first pipeline stage.
dat1s1 <= (dat1s0 < dat2s0) ? dat2s0 : dat1s0;
dat2s1 <= (dat1s0 < dat2s0) ? dat1s0 : dat2s0;
dat3s1 <= (dat3s0 < dat4s0) ? dat4s0 : dat3s0;
dat4s1 <= (dat3s0 < dat4s0) ? dat3s0 : dat4s0;
dat5s1 <= dat5s0;

// This implements the second pipeline stage.
dat1s2 <= dat1s1;
dat2s2 <= (dat2s1 < dat3s1) ? dat3s1 : dat2s1;
dat3s2 <= (dat2s1 < dat3s1) ? dat2s1 : dat3s1;
dat4s2 <= (dat4s1 < dat5s1) ? dat5s1 : dat4s1;
dat5s2 <= (dat4s1 < dat5s1) ? dat4s1 : dat5s1;

// This implements the third pipeline stage.
dat1s3 <= (dat1s2 < dat2s2) ? dat2s2 : dat1s2;
dat2s3 <= (dat1s2 < dat2s2) ? dat1s2 : dat2s2;
dat3s3 <= (dat3s2 < dat4s2) ? dat4s2 : dat3s2;
dat4s3 <= (dat3s2 < dat4s2) ? dat3s2 : dat4s2;
dat5s3 <= dat5s2;

// This implements the fourth pipeline stage.
dat1s4 <= dat1s3;
dat2s4 <= (dat2s3 < dat3s3) ? dat3s3 : dat2s3;
dat3s4 <= (dat2s3 < dat3s3) ? dat2s3 : dat3s3;
dat4s4 <= (dat4s3 < dat5s3) ? dat5s3 : dat4s3;
dat5s4 <= (dat4s3 < dat5s3) ? dat4s3 : dat5s3;

// This implements the fifth pipeline stage.
dat1s5 <= (dat1s4 < dat2s4) ? dat2s4 : dat1s4;
dat2s5 <= (dat1s4 < dat2s4) ? dat1s4 : dat2s4;
dat3s5 <= (dat3s4 < dat4s4) ? dat4s4 : dat3s4;
dat4s5 <= (dat3s4 < dat4s4) ? dat3s4 : dat4s4;
dat5s5 <= dat5s4;
end

// The output data is already registered, so all
// I have to do is drive it out of the module.
assign out1 = dat1s5;
assign out2 = dat2s5;
assign out3 = dat3s5;
assign out4 = dat4s5;
assign out5 = dat5s5;

endmodule

 

[Paul Uiterlinden]

Hi
I need a faster sort algorithm, which I got at
http://www.engr.sjsu.edu/crabill/ in lecture module5.

I am an ardent VHDL user. So I need to convert the verilog code to
VHDL.
I am attaching the code for convenience.

Not being a real Verilog user, see my first shot for translation
below.

Is there any VERILOG to VHDL converter available?
I could find VHDL to verilog converter in abundance but no verilog
to vhdl.
--------------------------------------------------------------------------------------------


`timescale 1 ns / 1 ps

module oetsort(clk, in1, in2, in3, in4, in5,
out1, out2, out3, out4, out5);
input clk;
input [15:0] in1, in2, in3, in4, in5;
output [15:0] out1, out2, out3, out4, out5;

LIBRARY ieee;
USE ieee.std_logic_1164.ALl;

ENTITY oetsort IS
PORT
(
...

reg [15:0] dat1s0, dat2s0, dat3s0, dat4s0, dat5s0;
reg [15:0] dat1s1, dat2s1, dat3s1, dat4s1, dat5s1;
reg [15:0] dat1s2, dat2s2, dat3s2, dat4s2, dat5s2;
reg [15:0] dat1s3, dat2s3, dat3s3, dat4s3, dat5s3;
reg [15:0] dat1s4, dat2s4, dat3s4, dat4s4, dat5s4;
reg [15:0] dat1s5, dat2s5, dat3s5, dat4s5, dat5s5;

SIGNAL dat1s0: std_logic_vector(15 DOWNTO 0);
...

always @(posedge clk)
begin

PROCESS
BEGIN
WAIT UNTIL clk = '1';

// This implements the input registers.
dat1s0 <= in1;
dat2s0 <= in2;
dat3s0 <= in3;
dat4s0 <= in4;
dat5s0 <= in5;

the same
...

// This implements the first pipeline stage.
dat1s1 <= (dat1s0 < dat2s0) ? dat2s0 : dat1s0;
dat2s1 <= (dat1s0 < dat2s0) ? dat1s0 : dat2s0;
dat3s1 <= (dat3s0 < dat4s0) ? dat4s0 : dat3s0;
dat4s1 <= (dat3s0 < dat4s0) ? dat3s0 : dat4s0;
dat5s1 <= dat5s0;

IF dat1s0 < dat2s0 THEN
dat1s1 <= dat2s0;
dat2s1 <= dat1s0;
ELSE
dat1s1 <= dat1s0;
dat2s1 <= dat2s0;
END IF;
...
dat5s1 <= dat5s0;

// This implements the second pipeline stage.
dat1s2 <= dat1s1;
dat2s2 <= (dat2s1 < dat3s1) ? dat3s1 : dat2s1;
dat3s2 <= (dat2s1 < dat3s1) ? dat2s1 : dat3s1;
dat4s2 <= (dat4s1 < dat5s1) ? dat5s1 : dat4s1;
dat5s2 <= (dat4s1 < dat5s1) ? dat4s1 : dat5s1;

// This implements the third pipeline stage.
dat1s3 <= (dat1s2 < dat2s2) ? dat2s2 : dat1s2;
dat2s3 <= (dat1s2 < dat2s2) ? dat1s2 : dat2s2;
dat3s3 <= (dat3s2 < dat4s2) ? dat4s2 : dat3s2;
dat4s3 <= (dat3s2 < dat4s2) ? dat3s2 : dat4s2;
dat5s3 <= dat5s2;

// This implements the fourth pipeline stage.
dat1s4 <= dat1s3;
dat2s4 <= (dat2s3 < dat3s3) ? dat3s3 : dat2s3;
dat3s4 <= (dat2s3 < dat3s3) ? dat2s3 : dat3s3;
dat4s4 <= (dat4s3 < dat5s3) ? dat5s3 : dat4s3;
dat5s4 <= (dat4s3 < dat5s3) ? dat4s3 : dat5s3;

// This implements the fifth pipeline stage.
dat1s5 <= (dat1s4 < dat2s4) ? dat2s4 : dat1s4;
dat2s5 <= (dat1s4 < dat2s4) ? dat1s4 : dat2s4;
dat3s5 <= (dat3s4 < dat4s4) ? dat4s4 : dat3s4;
dat4s5 <= (dat3s4 < dat4s4) ? dat3s4 : dat4s4;
dat5s5 <= dat5s4;
end

END PROCESS;

// The output data is already registered, so all
// I have to do is drive it out of the module.
assign out1 = dat1s5;
assign out2 = dat2s5;
assign out3 = dat3s5;
assign out4 = dat4s5;
assign out5 = dat5s5;

out1 <= dat1s5;
...

endmodule

END ENTITY oetsort;

 

[Ralf Hildebrandt]

Ved wrote:

I am an ardent VHDL user. So I need to convert the verilog code to
VHDL.
I am attaching the code for convenience.

module oetsort(clk, in1, in2, in3, in4, in5,
out1, out2, out3, out4, out5);
input clk;
input [15:0] in1, in2, in3, in4, in5;
output [15:0] out1, out2, out3, out4, out5;

Your task: The entity is really easy.

reg [15:0] dat1s0, dat2s0, dat3s0, dat4s0, dat5s0;

signal dat1s0, dat2s0, dat3s0, dat4s0, dat5s0 : std_ulogic_vector(15
downto 0);

.... and so on...

always @(posedge clk)
begin
// This implements the input registers.

process(clk)
if rising_edge(clk) then

dat1s0 <= in1;

Equal in VHDL.

.... and so on...

// This implements the first pipeline stage.
dat1s1 <= (dat1s0 < dat2s0) ? dat2s0 : dat1s0;

if (unsigned(dat1s0) < unsigned(dat2s0)) then
dat1s1 <= dat2s0;
else dat1s1 <= dat1s0;
end if;

.... and so on for the others ...

(Make sure, that unsigned() is the right conversion and not signed().)

....

end

end process;

// The output data is already registered, so all
// I have to do is drive it out of the module.
assign out1 = dat1s5;
assign out2 = dat2s5;
assign out3 = dat3s5;
assign out4 = dat4s5;
assign out5 = dat5s5;

out1 <= dat1s5;

.... and so on.

endmodule

end name_of_your_architecture;



Ralf

 

[a1_nocrap_exh]

if (unsigned(dat1s0) < unsigned(dat2s0)) then
dat1s1 <= dat2s0;
else dat1s1 <= dat1s0;
end if;

(Make sure, that unsigned() is the right conversion and not signed().)

...

It might be worth using ieee.std_logic_unsigned.all; in this small
block.

 

[Andy]

If the values represented by the slv's are numeric, they should be
numeric.signed or numeric.unsigned types in the first place,
eliminating the need for all the conversions during the comparisons.
That would be the preferred approach, especially over using a
non-standard package that differs from one vendor to the next.

Or my personal preference would be to use integer subtypes...

Andy

 

[Andy]

Oops, that should be numeric_std.signed or numeric_std.unsigned.

Andy

 

[Ved]

Thanks to all of you .