equivalent of defparam in vhdl.

Discussion in 'VHDL' started by kk, Aug 1, 2006.

  1. kk

    kk Guest

    For one of my program, i use defparam in verilog to set a parameter
    which is one level below the hierarchy. I've three modules A, B, C. The
    C is instantiated in B, B in A. There is a parameter in C which is not
    brought out to B. I dont have the permission to modify B and C by any
    chance. In verilog i can set the parameter by using a defparam
    statement in A.
    Is there way i could do this in VHDL, if all the three are in VHDL.

    thanks in adv.
    kk, Aug 1, 2006
    #1
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  2. kk

    Ajeetha Guest

    Hi KK,
    If this is for Synthesis, it is a bad style - usually defparam is
    unsupported in synth tools. If it is for pure simulation alone,
    simulators provide a way to override generics from command line.
    Typically the option is "-g".

    Read your tool's doc for more.

    HTH
    Ajeetha, CVC
    www.noveldv.com
    www.systemverilog.us

    kk wrote:
    > For one of my program, i use defparam in verilog to set a parameter
    > which is one level below the hierarchy. I've three modules A, B, C. The
    > C is instantiated in B, B in A. There is a parameter in C which is not
    > brought out to B. I dont have the permission to modify B and C by any
    > chance. In verilog i can set the parameter by using a defparam
    > statement in A.
    > Is there way i could do this in VHDL, if all the three are in VHDL.
    >
    > thanks in adv.
    Ajeetha, Aug 1, 2006
    #2
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  3. kk

    kk Guest

    Hi,

    First of this is only for simulation and not for synthesis.
    Secondly, i dont think i can use the -g option, as the problem is with
    wrapper + smart models rather than actual vhdl files.

    thanks....

    Ajeetha wrote:
    > Hi KK,
    > If this is for Synthesis, it is a bad style - usually defparam is
    > unsupported in synth tools. If it is for pure simulation alone,
    > simulators provide a way to override generics from command line.
    > Typically the option is "-g".
    >
    > Read your tool's doc for more.
    >
    > HTH
    > Ajeetha, CVC
    > www.noveldv.com
    > www.systemverilog.us
    >
    > kk wrote:
    > > For one of my program, i use defparam in verilog to set a parameter
    > > which is one level below the hierarchy. I've three modules A, B, C. The
    > > C is instantiated in B, B in A. There is a parameter in C which is not
    > > brought out to B. I dont have the permission to modify B and C by any
    > > chance. In verilog i can set the parameter by using a defparam
    > > statement in A.
    > > Is there way i could do this in VHDL, if all the three are in VHDL.
    > >
    > > thanks in adv.
    kk, Aug 2, 2006
    #3
  4. kk

    Rob Dekker Guest

    "Ajeetha" <> wrote in message news:...
    > Hi KK,
    > If this is for Synthesis, it is a bad style - usually defparam is
    > unsupported in synth tools.


    Actually defparam is supported for most synthesis tools that I know of.
    Although not without pain and suffering for the synthesis compiler implementers :eek:(

    Note that defparam is scheduled to be removed from the Verilog language..
    Not that that has much effect : it is used in almost all Verilog designs, due
    to the primitive start of Verilog.

    Rob
    Rob Dekker, Aug 4, 2006
    #4
  5. kk

    Rob Dekker Guest

    "kk" <> wrote in message news:...
    > For one of my program, i use defparam in verilog to set a parameter
    > which is one level below the hierarchy. I've three modules A, B, C. The
    > C is instantiated in B, B in A. There is a parameter in C which is not
    > brought out to B. I dont have the permission to modify B and C by any
    > chance. In verilog i can set the parameter by using a defparam
    > statement in A.
    > Is there way i could do this in VHDL, if all the three are in VHDL.
    >
    > thanks in adv.
    >


    From A you want to control a parameter in C, so that is TWO levels deep into the hierarchy.

    I believe that you can do this nicely with a configuration of A, although I have not tried it out :
    Here are the crucial parts of the configuration :

    configuration foo of A is
    ...
    for instance_name_of_B_in_A
    ..
    for instance_name_of_C_in_B
    use work.C generic map (Cs_parameter => As_param_value) ..
    end configuration ;

    I think As_param_value can even be an expression in terms of generics in either A or even B
    which are up in the hierarchy path when this configuration hits.
    That is because both B's and A's scope (name space) are made visible in the component configuration.

    This means that you can actually do more than the Verilog defparam.

    Rob
    Rob Dekker, Aug 4, 2006
    #5
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