Equivalent of SystemVerilog Interface in VHDL?

Discussion in 'VHDL' started by Poojan Wagh, Aug 23, 2010.

  1. Poojan Wagh

    Poojan Wagh Guest

    I was wondering if VHDL-2008 (or newer) includes an equivalent of the
    SystemVerilog interface.
    Poojan Wagh, Aug 23, 2010
    #1
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  2. On Mon, 23 Aug 2010 11:12:45 -0700 (PDT), Poojan Wagh wrote:

    > I was wondering if VHDL-2008 (or newer) includes an
    > equivalent of the SystemVerilog interface.


    hi Poojan,

    No, I don't think it does.

    Signals of record type have always been available, and
    allow you to do some of the simpler things you can do
    with SV interfaces, but you typically need to pass them
    through "inout" ports which rather messes things up.

    There have been various discussions in the past about
    adding directions to individual elements of a record,
    but (to the best of my knowledge) that never came to
    anything - it doesn't sound very nice anyway.

    I don't think it is a good idea to be excessively
    envious of SV's interfaces. They look like a really
    good idea on the surface, and they have some very
    interesting potential applications, but in SV as it
    stands today they are so badly broken that it's
    pretty much impossible to do anything really
    creative with them. (Yes, I can hear the mumblings
    in the back row even now... here goes Jonathan
    ranting about interfaces for the Nth time....
    yawn, yawn...)
    --
    Jonathan Bromley
    Jonathan Bromley, Aug 23, 2010
    #2
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  3. Poojan Wagh

    Poojan Wagh Guest

    On Aug 23, 1:57 pm, Jonathan Bromley <>
    wrote:

    > I don't think it is a good idea to be excessively
    > envious of SV's interfaces.  They look like a really
    > good idea on the surface, and they have some very
    > interesting potential applications, but in SV as it
    > stands today they are so badly broken that it's
    > pretty much impossible to do anything really
    > creative with them.  (Yes, I can hear the mumblings
    > in the back row even now... here goes Jonathan
    > ranting about interfaces for the Nth time....
    > yawn, yawn...)
    > --
    > Jonathan Bromley


    Apparently, I missed the last N-1 times. What's broken about SV
    interfaces? (Feel free to reply directly if this line of questioning
    is off-topic for this list.)
    Poojan Wagh, Aug 24, 2010
    #3
  4. On 8/24/2010 5:57 AM, Poojan Wagh wrote:

    > Apparently, I missed the last N-1 times. What's broken about SV
    > interfaces?


    That was in comp.lang.verilog

    -- Mike Treseler
    Mike Treseler, Aug 24, 2010
    #4
  5. Poojan Wagh

    JimLewis Guest

    On Aug 23, 11:12 am, Poojan Wagh <> wrote:
    > I was wondering if VHDL-2008 (or newer) includes an equivalent of the
    > SystemVerilog interface.


    I use records with resolved elements. I have written resolution
    functions for integer, real, and time to facilitate this. Not for
    RTL. Use it extensively in testbench models. Also cover it in our
    VHDL Testbenches and Verification class.

    Cheers,
    Jim
    SynthWorks VHDL Training
    JimLewis, Sep 8, 2010
    #5
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