P
Poojan Wagh
I was wondering if VHDL-2008 (or newer) includes an equivalent of the
SystemVerilog interface.
SystemVerilog interface.
I was wondering if VHDL-2008 (or newer) includes an
equivalent of the SystemVerilog interface.
I don't think it is a good idea to be excessively
envious of SV's interfaces. They look like a really
good idea on the surface, and they have some very
interesting potential applications, but in SV as it
stands today they are so badly broken that it's
pretty much impossible to do anything really
creative with them. (Yes, I can hear the mumblings
in the back row even now... here goes Jonathan
ranting about interfaces for the Nth time....
yawn, yawn...)
Apparently, I missed the last N-1 times. What's broken about SV
interfaces?
I was wondering if VHDL-2008 (or newer) includes an equivalent of the
SystemVerilog interface.
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