Error 10500

Discussion in 'VHDL' started by rain, Dec 10, 2011.

  1. rain

    rain

    Joined:
    Dec 10, 2011
    Messages:
    1
    Hey,
    I am new to VHDL and I need some help. I am trying to write a register file in VHDL. I keep getting error messages, below:
    Error (10500): VHDL syntax error at reg_file.vhd(45) near text "when"; expecting ";"
    Error (10500): VHDL syntax error at reg_file.vhd(56) near text "when"; expecting ";"
    Error (10500): VHDL syntax error at reg_file.vhd(66) near text "and"; expecting "(", or "'", or "."
    Info: Found 0 design units, including 0 entities, in source file reg_file.vhd
    Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
    Error: Peak virtual memory: 212 megabytes
    Error: Processing ended: Sat Dec 10 05:53:00 2011
    Error: Elapsed time: 00:00:02
    Error: Total CPU time (on all processors): 00:00:02
    Error: Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings

    This is my code:

    -- To make this project tractable, here we simply assume
    -- that the register file has 8 instructions.
    library ieee ;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    ---------------------------------------------------

    entity reg_file is
    port( clk: in std_logic;
    RegWrite: in std_logic;
    RsAddr: in std_logic_vector(4 downto 0);
    RtAddr: in std_logic_vector(4 downto 0);
    RdAddr: in std_logic_vector(4 downto 0);
    WriteData: in std_logic_vector(31 downto 0);
    Rs: out std_logic_vector(31 downto 0);
    Rt: out std_logic_vector(31 downto 0);

    -- the following 8 outputs are only for simulation purpose
    -- they are corresponding to the eight register words in
    -- the register file
    Reg_word_0: out std_logic_vector(31 downto 0); -- reg word 0
    Reg_word_1: out std_logic_vector(31 downto 0);
    Reg_word_2: out std_logic_vector(31 downto 0);
    Reg_word_3: out std_logic_vector(31 downto 0);
    Reg_word_4: out std_logic_vector(31 downto 0);
    Reg_word_5: out std_logic_vector(31 downto 0);
    Reg_word_6: out std_logic_vector(31 downto 0);
    Reg_word_7: out std_logic_vector(31 downto 0));
    end entity reg_file;
    ----------------------------------------------------

    architecture reg_file_arch of reg_file is

    begin

    Reg_word_0 <= "00000000000000000000000000000000";

    p0: process (RegWrite,RsAddr,RtAddr,RdAddr,clk) is

    begin

    if rising_edge (clk) and RegWrite='0' then

    Rs <= Reg_word_0 when RsAddr = "00000" else
    Reg_word_1 when RsAddr = "00001" else
    Reg_word_2 when RsAddr = "00010" else
    Reg_word_3 when RsAddr = "00011" else
    Reg_word_4 when RsAddr = "00100" else
    Reg_word_5 when RsAddr = "00101" else
    Reg_word_6 when RsAddr = "00110" else
    Reg_word_7;



    Rt <= Reg_word_0 when RtAddr = "00000" else
    Reg_word_1 when RtAddr = "00001" else
    Reg_word_2 when RtAddr = "00010" else
    Reg_word_3 when RtAddr = "00011" else
    Reg_word_4 when RtAddr = "00100" else
    Reg_word_5 when RtAddr = "00101" else
    Reg_word_6 when RtAddr = "00110" else
    Reg_word_7;


    elseif rising_edge(clk) and RegWrite='1' then

    if RdAddr= null then --for load functions

    case RtAddr is
    when "00001" => Reg_word_1 <= WriteData;
    when "00010" => Reg_word_2 <= WriteData;
    when "00011" => Reg_word_3 <= WriteData;
    when "00100" => Reg_word_4 <= WriteData;
    when "00101" => Reg_word_5 <= WriteData;
    when "00110" => Reg_word_6 <= WriteData;
    when others => Reg_word_7 <= WriteData;
    end case;
    else
    case RdAddr is --other write instructions write to the register specified by RdAddr.
    when "00001" => Reg_word_1 <= WriteData;
    when "00010" => Reg_word_2 <= WriteData;
    when "00011" => Reg_word_3 <= WriteData;
    when "00100" => Reg_word_4 <= WriteData;
    when "00101" => Reg_word_5 <= WriteData;
    when "00110" => Reg_word_6 <= WriteData;
    when others => Reg_word_7 <= WriteData;
    end case;
    end if;
    end if;
    end process p0;
    end architecture reg_file_arch;

    I would appreciate any help... thanks. :)
     
    rain, Dec 10, 2011
    #1
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