ERROR:HDLParsers:164 - "D:/Deepak jena/full_adder/fa.vhd" Line 51. parse error, unexp

Discussion in 'VHDL' started by dkjena1, Jun 7, 2011.

  1. dkjena1

    dkjena1

    Joined:
    Jun 7, 2011
    Messages:
    1
    I am using XILINX ISE 8.1i software and writing code for full adder in structural model. This is my code......


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity fa is
    Port ( a,b,cin : in STD_LOGIC;
    s,co : out STD_LOGIC);
    end fa;

    architecture Behavioral of fa is
    component andgate
    port(a1,b1:in std_logic;c1:eek:ut std_logic);
    end component;
    component xorgate
    port(a2,b2:in std_logic;c2:eek:ut std_logic);
    end component;
    component orgate
    port(a3,b3:in std_logic;c3:eek:ut std_logic);
    end component;
    signal x1,x2,x3:std_logic;
    begin
    xo1: xorgate portmap(a,b,x1);
    xo2: xorgate portmap(cin,x1,s);
    a1: andgate portmap(a,b,x3);
    a2: andgate portmap(cin,x1,x2);
    o1: orgate portmap(x2,x3,co);
    end Behavioral;


    In this program Syntax check fails and show the following error. can any body help me to solve the problem?


    ERROR:HDLParsers:164 - "D:/Deepak jena/full_adder/fa.vhd" Line 51. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACK

    Process "Check Syntax" failed
     
    dkjena1, Jun 7, 2011
    #1
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  2. dkjena1

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    A space is required between 'port' and 'map'
     
    joris, Jun 8, 2011
    #2
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