Error in modelSim

Discussion in 'VHDL' started by snehalatha, Mar 23, 2010.

  1. snehalatha

    snehalatha

    Joined:
    Mar 23, 2010
    Messages:
    1
    Hello,

    wrote the following architecture in the test bench and I am getting the following error.

    library IEEE;
    use IEEE.Std_Logic_1164.all;

    entity T_DDRV4 is
    end T_DDRV4;

    architecture TEST of T_DDRV4 is

    component DDRV4

    port (
    ALARM_TIME_MS_HR : in std_logic_vector (3 downto 0);
    CURRENT_TIME_MS_HR : in std_logic_vector (3 downto 0);
    SHOW_A : in std_logic;
    ALARM_TIME_LS_HR : in std_logic_vector (3 downto 0);
    CURRENT_TIME_LS_HR : in std_logic_vector (3 downto 0);
    ALARM_TIME_MS_MIN : in std_logic_vector (3 downto 0);
    CURRENT_TIME_MS_MIN : in std_logic_vector (3 downto 0);
    ALARM_TIME_LS_MIN : in std_logic_vector (3 downto 0);
    CURRENT_TIME_LS_MIN : in std_logic_vector (3 downto 0);
    SOUND_ALARM : out std_logic;
    DISPLAY_TIME_MS_HR : out std_logic_vector (6 downto 0);
    DISPLAY_TIME_LS_HR : out std_logic_vector (6 downto 0);
    DISPLAY_TIME_MS_MIN : out std_logic_vector (6 downto 0);
    DISPLAY_TIME_LS_MIN : out std_logic_vector (6 downto 0)
    );
    end component;
    signal T_ALARM_TIME_MS_HR : std_logic_vector (3 downto 0);
    signal T_CURRENT_TIME_MS_HR : std_logic_vector (3 downto 0);
    signal T_SHOW_A : std_logic;
    signal T_SOUND_ALARM : std_logic;
    signal T_DISPLAY_TIME_MS_HR : std_logic_vector (6 downto 0);
    signal T_ALARM_TIME_LS_HR : std_logic_vector (3 downto 0);
    signal T_CURRENT_TIME_LS_HR : std_logic_vector (3 downto 0);
    signal T_DISPLAY_TIME_LS_HR : std_logic_vector (6 downto 0);
    signal T_ALARM_TIME_MS_MIN : std_logic_vector (3 downto 0);
    signal T_CURRENT_TIME_MS_MIN : std_logic_vector (3 downto 0);
    signal T_DISPLAY_TIME_MS_MIN : std_logic_vector (6 downto 0);
    signal T_ALARM_TIME_LS_MIN : std_logic_vector (3 downto 0);
    signal T_CURRENT_TIME_LS_MIN : std_logic_vector (3 downto 0);
    signal T_DISPLAY_TIME_LS_MIN : std_logic_vector (6 downto 0);

    begin
    uut : DDRV4 port map (

    ALARM_TIME_MS_HR => T_ALARM_TIME_MS_HR,
    CURRENT_TIME_MS_HR => T_CURRENT_TIME_MS_HR,
    SHOW_A => T_SHOW_A,
    SOUND_ALARM => T_SOUND_ALARM,
    DISPLAY_TIME_MS_HR => T_DISPLAY_TIME_MS_HR,

    ALARM_TIME_LS_HR => T_ALARM_TIME_LS_HR,
    CURRENT_TIME_LS_HR => T_CURRENT_TIME_LS_HR,
    DISPLAY_TIME_LS_HR => T_CURRENT_TIME_LS_HR,

    ALARM_TIME_MS_MIN => T_ALARM_TIME_LS_HR,
    CURRENT_TIME_MS_MIN => T_CURRENT_TIME_MS_MIN,
    DISPLAY_TIME_MS_MIN => T_DISPLAY_TIME_MS_MIN,

    ALARM_TIME_LS_MIN => T_ALARM_TIME_LS_MIN,
    CURRENT_TIME_LS_MIN => T_CURRENT_TIME_LS_MIN,
    DISPLAY_TIME_LS_MIN => T_DISPLAY_TIME_LS_MIN
    );
    The error while i was simulating is

    # ** Error: (vsim-3173) Entity 'work.t_ddrv4' has no architecture.
    I got the results for other test benches but not this one.
    Please help.
     
    snehalatha, Mar 23, 2010
    #1
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