error in synthesis in vhdl code...

Discussion in 'VHDL' started by priyanka24, Apr 20, 2012.

  1. priyanka24

    priyanka24

    Joined:
    Jan 26, 2012
    Messages:
    4
    Hi...

    i have written VHDL code and got simulated correctly.

    but getting following error during synthesis::


    ERROR:Xst:787 : line 98: Index value <9> is not in Range of array <output_stream>.


    what is solution for this plz help me?????
    priyanka24, Apr 20, 2012
    #1
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  2. priyanka24

    sridars

    Joined:
    Apr 21, 2012
    Messages:
    1
    Hi, You must have created 8 bit array and assigning the value to 9th bit of same array.
    post the code if possible
    sridars, Apr 21, 2012
    #2
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