Error "Unsupported Clock Statement" when asigning a value to a signal

Discussion in 'VHDL' started by Georg Gläser, Feb 8, 2006.

  1. Hi there!
    I've written a piece of VHDL-code in Xilinx ISE 8.1 WebPack, that should
    hold an output high for 330 ns (clock 18MHz). I get an error that i have an
    unsupported Clock statement in my code in a line where I'm only trying to
    assign a value to a signal. Can you help me?

    Here is my code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity lphold is
    Port ( clk : in STD_LOGIC;
    set : in STD_LOGIC;
    lp : out STD_LOGIC);
    end lphold;

    architecture Behavioral of lphold is
    signal count: std_logic_vector(0 to 1):="00";
    signal lp_tmp: std_logic := '0';
    begin
    process(clk, set)
    begin
    if (set = '1') then
    lp_tmp <= '1';
    elsif (rising_edge(clk) and set = '1') then
    count <= count + 1;
    if (count = "10") then
    count <= "00";
    end if;
    elsif (count = "00") then
    lp_tmp <= '0';
    end if;
    end process;
    lp <= lp_tmp;


    Many Thx for each answer!
    Georg


    end Behavioral;
     
    Georg Gläser, Feb 8, 2006
    #1
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  2. I forgot sth. . . . the error occurs on "lp_tmp <= '1';"
    I still don't know why . . .
     
    Georg Gläser, Feb 8, 2006
    #2
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  3. Georg Gläser

    Peter Guest

    >
    > architecture Behavioral of lphold is
    > signal count: std_logic_vector(0 to 1):="00";
    > signal lp_tmp: std_logic := '0';
    > begin
    > process(clk, set)
    > begin
    > if (set = '1') then
    > lp_tmp <= '1';
    > elsif (rising_edge(clk) and set = '1') then
    > count <= count + 1;
    > if (count = "10") then
    > count <= "00";
    > end if;
    > elsif (count = "00") then
    > lp_tmp <= '0';
    > end if;
    > end process;
    > lp <= lp_tmp;
    >


    Hi,

    There are some strange things in your code:

    If set = '1' -- Asynchronous set has highest priority
    Elsif rising_edge(clk) AND set = '1' -- Gated clock with asynchronous
    set??
    --
    --
    Elsif (count ="00") ... -- To be executed in absence of
    -- asynchronous set or
    -- rising edge of clock??

    These kind of problems may be avoided if you use a
    synchronous template:

    Process(clk,reset)
    Begin
    if reset='1' then
    -- Initialize all signals
    elsif rising_edge(clk) then
    if something then
    ---
    elsif something_else then
    ---
    end if
    --
    end if;
    -- Nothing more here!
    End process;

    Everything after the "elsif rising_edge" will generate synchronous
    logic.
    The only asychronous part is the initialization of all signals.

    Regards, Peter
     
    Peter, Feb 8, 2006
    #3
  4. Georg Gläser

    deshya

    Joined:
    Apr 3, 2009
    Messages:
    4
    When I compile the following code I get an error message saying "Unsupported clock statement" I cannot figure out why? Thanks in advance
    ----------------------------------------------------------------------------------
    entity cpu is
    Port ( AR : inout STD_LOGIC_VECTOR (15 downto 0);
    PC : inout STD_LOGIC_VECTOR (15 downto 0);
    DR : inout STD_LOGIC_VECTOR (7 downto 0);
    TR : inout STD_LOGIC_VECTOR (7 downto 0);
    IR : inout STD_LOGIC_VECTOR (7 downto 0);
    R : inout STD_LOGIC_VECTOR (7 downto 0);
    AC : inout STD_LOGIC_VECTOR (7 downto 0);
    Mem : inout STD_LOGIC_VECTOR (15 downto 0);
    path : inout STD_LOGIC_VECTOR (15 downto 0);
    clk : in STD_LOGIC;
    sel : in STD_LOGIC_VECTOR(3 downto 0);
    display :eek:ut STD_LOGIC_VECTOR(9 downto 0));
    end cpu;

    architecture Behavioral of cpu is

    TYPE matrix IS ARRAY(0 to 42,9 downto 0)of STD_LOGIC;
    signal microseq:matrix:= (('1','0','0','0','0','0','0','0','1','0'), ('0','0','0','0','0','0','1','0','0','0'), ('1','0','0','0','0','0','1','0','0','0'),
    ('0','0','0','0','0','0','1','0','0','1'), ('0','0','0','0','0','0','1','0','0','0'), ('0','1','0','1','0','0','0','0','1','0'), ('0','0','0','0','0','0','1','0','0','0'), ('0','0','1','0','0','0','0','0','0','0'),
    ('0','0','0','0','0','0','1','0','0','0'), ('0','0','0','0','0','0','1','0','0','0'), ('0','1','0','1','0','0','0','0','1','0'), ('0','0','0','0','0','1','0','0','0','0'), ('0','0','1','0','0','0','1','0','0','0'),
    ('0','0','0','0','0','1','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'),
    ('0','0','0','0','1','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'),
    ('0','0','0','0','0','0','1','0','0','1'), ('0','0','0','0','0','0','1','0','0','0'), ('0','1','0','1','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'),
    ('0','0','0','0','0','0','1','0','0','1'), ('0','0','0','0','0','0','1','0','0','0'), ('0','1','0','1','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'),
    ('0','0','0','0','0','0','1','0','0','1'), ('0','0','0','0','0','0','1','0','0','0'), ('0','1','0','1','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'),
    ('0','0','0','0','1','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'), ('0','0','0','0','0','0','0','0','0','0'));
    signal temp : std_logic_vector(9 downto 0);
    signal index : integer;
    signal j: integer;
    signal i:integer;
    signal k:integer;
    signal z : std_logic;

    begin
    process(clk, temp, index,j,i,z) begin

    while(rising_edge(clk)) loop

    -- 3 Fetch cycles
    for y in 0 to 2 loop

    j <= y;

    for a in 0 to 9 loop
    temp(a) <= microseq (j,a);
    end loop;

    display <= temp;


    if(microseq(j,9)='1') then

    AR <= PC;

    end if;

    if(microseq(j,3)='1') then

    TR <= DR;
    DR <= Mem(7 downto 0);

    end if;

    end loop;

    --Microsequencer
    index <= conv_integer((sel*"0101")+ "0011");

    for m in 0 to 4 loop

    i <= m;

    while(temp /= "00000000000") loop

    k<=index+i;

    for b in 0 to 9 loop
    temp(b) <= microseq(k,b);
    end loop;

    --DRHBUS
    if(microseq(i,8)='1') then

    path(15 downto 8) <= DR;

    end if;

    --DRLBUS
    if(microseq(i,7)='1') then

    path(7 downto 0) <= DR;

    end if;

    --TRBUS
    if(microseq(i,6)='1') then

    path(7 downto 0) <= TR;

    end if;

    --RBUS
    if(microseq(i,5)='1') then

    path(7 downto 0) <= R;

    end if;

    --ACBUS
    if(microseq(i,4)='1') then

    path(7 downto 0) <= AC;

    end if;

    --MEMBUS
    if(microseq(i,3)='1') then

    TR <= DR;
    DR <= Mem(7 downto 0);

    end if;

    --BUSMEM
    if(microseq(i,2)='1') then

    Mem(7 downto 0) <= path(7 downto 0);

    end if;

    --ARLOAD
    if(microseq(i,1)='1') then

    AR <= path;

    end if;

    --ARINC
    if(microseq(i,0)='0') then

    AR <= AR + "0000000000000001";

    end if;

    --SELECT

    case sel is

    when "0000" =>

    if(i = 0 or i= 1) then

    PC<=PC+"0000000000000001";

    elsif(i=2)then

    AR <= path;

    elsif(i=4)then

    AC <= path(7 downto 0);

    end if;

    when "0001" =>

    if(i =0 or i= 1) then

    PC<=PC+"0000000000000001";

    elsif(i=2)then

    AR <= path;

    elsif(i=3)then

    DR <= path(7 downto 0);

    end if;

    when "0010" => R <= path(7 downto 0);

    when "0011" => AC <= path(7 downto 0);

    when "0100"=>

    if(i=3) then

    PC <= path;

    end if;

    when "0101" =>

    if(Z = '0') then

    if(i=3) then

    PC <= path;

    end if;

    end if;

    when "0110" =>

    if(Z = '1') then

    if(i=3) then

    PC <= path;

    end if;

    end if;

    when others => path <= "0000000000000000";

    end case;

    end loop;

    end loop;

    end loop;

    end process;

    end Behavioral;
     
    deshya, Apr 3, 2009
    #4
  5. Georg Gläser

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    "while(rising_edge(clk)) loop"

    rising_edge(clk) is an event, not a state. I don't see how you can use it in a while loop.

    if rising_edge(clk) and (clk = '1') then
    while (???) loop
    - 3 Fetch cycles
    ...
     
    JohnDuq, Apr 3, 2009
    #5
  6. Georg Gläser

    deshya

    Joined:
    Apr 3, 2009
    Messages:
    4
    thank you, it took off the error
     
    deshya, Apr 3, 2009
    #6
  7. Georg Gläser

    deshya

    Joined:
    Apr 3, 2009
    Messages:
    4
    Connecting entities

    Wondering how several entities could be called and connected within a programm(an architecture of another entitiy)
     
    deshya, Apr 5, 2009
    #7
  8. Georg Gläser

    Ukanbal

    Joined:
    Mar 7, 2009
    Messages:
    9
    for that deshya you need to use portmapping
    most of the programs do automatic connection after port mapping if you select the entities (their vhd or vhdl codes) you want to use as a part of the project you are creating. So basically all you have to do is do the port mapping for the entities you want to use inside the main entity and create the signals required for inter connectivity.
     
    Ukanbal, Apr 6, 2009
    #8
  9. Georg Gläser

    Ukanbal

    Joined:
    Mar 7, 2009
    Messages:
    9
    an example i guess will make it easier for you. so here it comes... lets assume you want to write the vhdl code for a datapath.

    ENTITY Dpath IS
    PORT(
    whatever declerations you have to make
    );
    End Dpath;

    ARCHITECTURE desc OF Dpath IS

    ---here you start declaring the components you are going to use such as

    Component pc
    PORT( clr : IN STD_LOGIC;
    clk : IN STD_LOGIC;
    ld : IN STD_LOGIC;
    inc : IN STD_LOGIC;
    d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    q : BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0));
    END Component;

    --- after you declare all the components you declare the signals you want to use

    (Signals go here)

    BEGIN

    ---and then you portmap all the signals of components

    pc_count : pc
    PORT MAP (
    clr => Clr_PC,
    clk => Clk,
    ld =>Ld_PC,
    inc =>Inc_PC,
    d => AM_out,
    q => Out_PC);

    the first part are the signals inside your actual component and the second ones are the declaration inside your new entity.

    i hope it helps.
     
    Ukanbal, Apr 6, 2009
    #9
  10. Georg Gläser

    deshya

    Joined:
    Apr 3, 2009
    Messages:
    4
    thanks a lot
     
    deshya, Apr 7, 2009
    #10
  11. Georg Gläser

    kushal

    Joined:
    Jul 5, 2012
    Messages:
    4
    unsupported clock statement error !! plz help ..

    hi ... in the specified line, iam getting unsupported clock statement error while synthesizing the code.. simulation worked well but this error is shown during synthesis. plz help as im not able to figure out why ..

    process(b_clkx8)
    begin
    if((rising_edge(b_clkx8)) and (state = idle) and (rxd_data = '0') ) then
    state <= start_detected;
    elsif((rising_edge(b_clkx8)) and (state = start_detected)
    and (rxd_data = '0') and (ct1 = 3)) then
    state <= recv_data; ----------------------------------------------
    elsif(((rising_edge(b_clkx8)) and (rxd_data = '1')
    and (ct1=0) and (ct2=0)) or((state = recv_data)
    and (ct1 = 7) and (ct2 = 9))) then
    state <= idle;
    end if;
    end process;
     
    kushal, Jul 5, 2012
    #11
  12. Georg Gläser

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    What logic family are you synthesizing for? You might try simplifying your clock statement first. Change:

    if((rising_edge(b_clkx) and (state = idle) and (rxd_data = '0') ) then

    to

    if((rising_edge(b_clkx)) then
    if((state = idle) and (rxd_data = '0') ) then


    Also, it shouldn't matter for synthesis, but I'm surprised you got away with it for simulation; your process line should read:

    process( b_clkx, state, rxd_data, start_detected, ct1, recv_data, ct2, idle)
     
    Last edited: Jul 9, 2012
    JohnDuq, Jul 9, 2012
    #12
  13. Georg Gläser

    kushal

    Joined:
    Jul 5, 2012
    Messages:
    4
    hi
    thnx for replying to my post. I want d code to be synthesizible for spartan 6 or spartan 3A. I changed d code as per your suggestion and the error isnt der anymore. Also after synthesis, i got some warnings. so is it ok to proceed or i shd try to remove dose warnings as well ?? Im new to VHDL so not sure which statements are synthesizible and which are not. plz help me which sites or texts should i go thru to be perfect in synthesizing d code rather dan only simulating. der seems to be many differences in code for sim and synth. i exatly donno which codes are synthesizible and which are not.
     
    Last edited: Jul 12, 2012
    kushal, Jul 12, 2012
    #13
  14. Georg Gläser

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    A lot of subtleties like this are device specific, so you have to see where the issues arise and figure out another way to do what you want. Warnings mean something isn't optimum; it is up to you to decide if it is worth perfecting; what are the consequences of leaving it as-is?

    This is a great site for posting questions; there are a lot of users who are much better experts than I am. For device specific questions like this clocking issue, I'd try the Xilinx forum (http://forums.xilinx.com/t5/Silicon-Devices/ct-p/SILICON). I've only posted CPLD questions there but that group is very knowledgeable.

    Happy coding!
     
    JohnDuq, Jul 12, 2012
    #14
  15. Georg Gläser

    kushal

    Joined:
    Jul 5, 2012
    Messages:
    4
    thnx for d forum .. hope i can gain some knowledge thru that forum .. one more thing, you said d process line should read:

    process( b_clkx, state, rxd_data, start_detected, ct1, recv_data, ct2, idle)

    instead of

    process(b_clkx)

    but i thought as i was monitoring the d other signals for all b_clkx edges i thought d sensitivity list is sufficient with b_clkx. Is it right dis way or der is some more reasoning attaced to create sensitivity list. please help me out in this matter..
     
    kushal, Jul 12, 2012
    #15
  16. Georg Gläser

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    If those are local (combinatorial) variables you need them in the process line. If they are synchronized to the d clock then you might be okay.

    As I understand it, the process block will only be processed when one of the variables (signals) in the process parameter list changes. If a variable changes and is not in the list it will be ignored until a variable in the list changes.
     
    JohnDuq, Jul 12, 2012
    #16
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