Error: (vcom-11) Could not find work.const

[max.giacometti]

Hi everybody!
I'm trying to simulate my design (created using ISE) but I found
several problems.
VHDL code was originally written under ISE 6.1, then I passed to ISE
8.1. It worked good until a translate error occurred, and then I was
unable to execute any translate operation.
So I created a new project, copying all .vhd files I needed. Now ISE
gives me no error, but under Modelsim (XE III/Starter 3.0d) the
following error occurs:

# -- Loading package std_logic_unsigned
# ** Error: (vcom-11) Could not find work.const.
# ** Error: TOP_test.vhw(25): Cannot find expanded name: work.const.
# ** Error: TOP_test.vhw(25): Unknown record element "const".
# -- Loading package textio
# -- Loading package std_logic_textio
# ** Error: TOP_test.vhw(29): VHDL Compiler exiting
# ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.
# Error in macro ./TOP_test.ndo line 7
# C:/Modeltech_xe_starter/win32xoem/vcom failed.
# while executing
# "vcom -explicit -93 "TOP_test.vhw""

"TOP_test" is the name of .tbw file I wanna run;
"const" is the name of the VHDL package that contains all parameters I
need.

What can I do?

Thanks

Max

 

[Jonathan Bromley]

# -- Loading package std_logic_unsigned
# ** Error: (vcom-11) Could not find work.const. [...]
"TOP_test" is the name of .tbw file I wanna run;
"const" is the name of the VHDL package that contains all parameters I
need.

What can I do?

Compile the package first?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[max.giacometti]

Jonathan Bromley ha scritto:

Compile the package first?

Under ISE 8.1 I didn't find the way to do that; I can't even check
package sintax.

Max

 

[Jonathan Bromley]

Jonathan Bromley ha scritto:


Under ISE 8.1 I didn't find the way to do that; I can't even check
package sintax.

I seem to remember that ISE lets you specify what kind
of VHDL each file represents - design, testbench or package.
I assume that it handles packages correctly if you tell
it about them.

Alternatively, you could stop fooling around with ISE to drive
the simulator, and do it properly from the simulator command
line

vcom mypackage.vhd
vcom mydesign.vhd
vcom mytestbench.vhd
vsim testbench
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.