Error which Don't know how to solve... newbie

Discussion in 'VHDL' started by pplnet, Dec 4, 2009.

  1. pplnet

    pplnet

    Joined:
    Dec 4, 2009
    Messages:
    4
    Everyone expert here please help me... I'm new to this.. but these problem I really dunno how to solve... Thx everyone!



    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity Sobel_vhdl is
    Port(
    Xnm1Ynm1 : in std_logic_vector ( 7 downto 0 );
    XnYnm1 : in std_logic_vector ( 7 downto 0 );
    Xnp1Ynm1 : in std_logic_vector ( 7 downto 0 );
    Xnm1Yn : in std_logic_vector ( 7 downto 0 );
    XnYn : in std_logic_vector ( 7 downto 0 );
    Xnp1Yn : in std_logic_vector ( 7 downto 0 );
    Xnm1Ynp1 : in std_logic_vector ( 7 downto 0 );
    XnYnp1 : in std_logic_vector ( 7 downto 0 );
    Xnp1Ynp1 : in std_logic_vector ( 7 downto 0 );
    ydata_out : out std_logic_vector ( 7 downto 0 ));
    end Sobel_vhdl;

    architecture Behavioral of Sobel_vhdl is
    signal op_int_vaL1 : std_logic_vector ( 10 downto 0 );
    signal op_int_vaL2 : std_logic_vector ( 10 downto 0 );
    signal op_vaL1 : std_logic_vector ( 10 downto 0 );
    signal op_vaL2 : std_logic_vector ( 10 downto 0 );
    signal abs_op_cal_val : std_logic_vector ( 10 downto 0 );

    constant Xnm1Ynm1VaL1 : integer := -1;
    constant XnYnm1VaL1 : integer := 0;
    constant Xnp1Ynm1VaL1 : integer := 1;
    constant Xnm1YnVaL1 : integer := -2;
    constant XnYnVaL1 : integer := 0;
    constant Xnp1YnVaL1 : integer := 2;
    constant Xnm1Ynp1VaL1 : integer := -1;
    constant XnYnp1VaL1 : integer := 0;
    constant Xnp1Ynp1VaL1 : integer := 1;

    constant Xnm1Ynm1VaL2 : integer := -1;
    constant XnYnm1VaL2 : integer := -2;
    constant Xnp1Ynm1VaL2 : integer := -1;
    constant Xnm1YnVaL2 : integer := 0;
    constant XnYnVaL2 : integer := 0;
    constant Xnp1YnVaL2 : integer := 0;
    constant Xnm1Ynp1VaL2 : integer := 1;
    constant XnYnp1VaL2 : integer := 2;
    constant Xnp1Ynp1VaL2 : integer := 1;


    begin
    op_int_vaL1 <= Xnm1Ynm1VaL1*CONV_INTEGER(Xnm1Ynm1) + XnYnm1VaL1*CONV_INTEGER(XnYnm1) + Xnp1Ynm1VaL1*CONV_INTEGER(Xnp1Ynm1)
    + Xnm1YnVaL1*CONV_INTEGER(Xnm1Yn) + XnYnVaL1*CONV_INTEGER(XnYn) + Xnp1YnVaL1*CONV_INTEGER(Xnp1Yn)
    + Xnm1Ynp1VaL1*CONV_INTEGER(Xnm1Ynp1) + XnYnp1VaL1*CONV_INTEGER(XnYnp1) + Xnp1Ynp1VaL1*CONV_INTEGER(Xnp1Ynp1);

    op_int_vaL2 <= Xnm1Ynm1VaL2*CONV_INTEGER(Xnm1Ynm1) + XnYnm1VaL2*CONV_INTEGER(XnYnm1) + Xnp1Ynm1VaL2*CONV_INTEGER(Xnp1Ynm1)
    + Xnm1YnVaL2*CONV_INTEGER(Xnm1Yn) + XnYnVaL2*CONV_INTEGER(XnYn) + Xnp1YnVaL2*CONV_INTEGER(Xnp1Yn)
    + Xnm1Ynp1VaL2*CONV_INTEGER(Xnm1Ynp1) + XnYnp1VaL2*CONV_INTEGER(XnYnp1) + Xnp1Ynp1VaL2*CONV_INTEGER(Xnp1Ynp1);

    op_vaL1 <= CONV_STD_LOGIC_VECTOR(op_int_vaL1, op_vaL1'length);
    op_vaL2 <= CONV_STD_LOGIC_VECTOR(op_int_vaL2, op_vaL2'length);

    process(op_vaL1) begin
    if op_vaL1(op_vaL1'left)='1' then -- 負の値
    abs_op_cal_vaL1 <= not(op_vaL1 -1);
    else -- 正の数
    abs_op_cal_vaL1 <= op_vaL1;
    end if;
    end process;
    process(op_vaL2) begin
    if op_vaL2(op_vaL2'left)='1' then -- 負の値
    abs_op_cal_vaL2 <= not(op_vaL2 -1);
    else -- 正の数
    abs_op_cal_vaL2 <= op_vaL2;
    end if;
    end process;
    abs_op_cal_val <= abs_op_cal_vaL1 + abs_op_cal_vaL2;

    ydata_out <= x"00" when h_valid_flag='0' or v_valid_flag='0' else
    x"FF" when (abs_op_cal_val(12) or abs_op_cal_val(11) or abs_op_cal_val(10) or abs_op_cal_val(9) or abs_op_cal_val(8))='1'
    else abs_op_cal_val(7 downto 0); -- 飽和演算

    end Behavioral;

    * HDL Compilation *

    =========================================================================

    Compiling vhdl file "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" in Library work.

    Entity <sobel_vhdl> compiled.

    ERROR:HDLParsers:800 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 75. Type of op_int_vaL1 is incompatible with type of +.

    ERROR:HDLParsers:800 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 79. Type of op_int_vaL2 is incompatible with type of +.

    ERROR:HDLParsers:808 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 81. CONV_STD_LOGIC_VECTOR can not have such operands in this context.

    ERROR:HDLParsers:808 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 82. CONV_STD_LOGIC_VECTOR can not have such operands in this context.

    ERROR:HDLParsers:3312 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 86. Undefined symbol 'abs_op_cal_vaL1'.

    ERROR:HDLParsers:1209 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 88. abs_op_cal_vaL1: Undefined symbol (last report in this block)

    ERROR:HDLParsers:3312 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 93. Undefined symbol 'abs_op_cal_vaL2'.

    ERROR:HDLParsers:1209 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 95. abs_op_cal_vaL2: Undefined symbol (last report in this block)

    ERROR:HDLParsers:3312 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 98. Undefined symbol 'abs_op_cal_vaL1'.

    ERROR:HDLParsers:1209 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 98. abs_op_cal_vaL1: Undefined symbol (last report in this block)

    ERROR:HDLParsers:3312 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 98. Undefined symbol 'abs_op_cal_vaL2'.

    ERROR:HDLParsers:1209 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 98. abs_op_cal_vaL2: Undefined symbol (last report in this block)

    ERROR:HDLParsers:3312 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 100. Undefined symbol 'h_valid_flag'.

    ERROR:HDLParsers:1209 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 100. h_valid_flag: Undefined symbol (last report in this block)

    ERROR:HDLParsers:3312 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 100. Undefined symbol 'v_valid_flag'.

    ERROR:HDLParsers:1209 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 100. v_valid_flag: Undefined symbol (last report in this block)

    ERROR:HDLParsers:3367 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 101. 12 is not included in the index range, 10 downto 0, of array abs_op_cal_val.

    ERROR:HDLParsers:3367 - "C:/Documents and Settings/Lawrence/Sobel_vhdl/Sobel_vhdl.vhd" Line 101. 11 is not included in the index range, 10 downto 0, of array abs_op_cal_val.
    pplnet, Dec 4, 2009
    #1
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  2. pplnet

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    You should be careful to use integer (or perhaps unsigned) consistently;
    When using integers, you should specify ranges (otherwise support for full 32-bit values will be generated! during synthesis)

    I think this is what was intended: (Obviously I didn't do any testing for correctness, only made necessary minimal changes to get it to build)

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
    
    entity Sobel_vhdl is
    Port(
    Xnm1Ynm1 : in std_logic_vector ( 7 downto 0 );
    XnYnm1 : in std_logic_vector ( 7 downto 0 );
    Xnp1Ynm1 : in std_logic_vector ( 7 downto 0 );
    Xnm1Yn : in std_logic_vector ( 7 downto 0 );
    XnYn : in std_logic_vector ( 7 downto 0 );
    Xnp1Yn : in std_logic_vector ( 7 downto 0 );
    Xnm1Ynp1 : in std_logic_vector ( 7 downto 0 );
    XnYnp1 : in std_logic_vector ( 7 downto 0 );
    Xnp1Ynp1 : in std_logic_vector ( 7 downto 0 );
    ydata_out : out std_logic_vector ( 7 downto 0 ));
    end Sobel_vhdl;
    
    architecture Behavioral of Sobel_vhdl is
    signal op_int_vaL1 : integer;
    signal op_int_vaL2 : integer;
    signal op_vaL1 : std_logic_vector ( 10 downto 0 );
    signal op_vaL2 : std_logic_vector ( 10 downto 0 );
    signal abs_op_cal_val1 : integer;
    signal abs_op_cal_val2 : integer;
    signal abs_op_cal_val : std_logic_vector ( 12 downto 0 );
    
    constant Xnm1Ynm1VaL1 : integer := -1;
    constant XnYnm1VaL1 : integer := 0;
    constant Xnp1Ynm1VaL1 : integer := 1;
    constant Xnm1YnVaL1 : integer := -2;
    constant XnYnVaL1 : integer := 0;
    constant Xnp1YnVaL1 : integer := 2;
    constant Xnm1Ynp1VaL1 : integer := -1;
    constant XnYnp1VaL1 : integer := 0;
    constant Xnp1Ynp1VaL1 : integer := 1;
    
    constant Xnm1Ynm1VaL2 : integer := -1;
    constant XnYnm1VaL2 : integer := -2;
    constant Xnp1Ynm1VaL2 : integer := -1;
    constant Xnm1YnVaL2 : integer := 0;
    constant XnYnVaL2 : integer := 0;
    constant Xnp1YnVaL2 : integer := 0;
    constant Xnm1Ynp1VaL2 : integer := 1;
    constant XnYnp1VaL2 : integer := 2;
    constant Xnp1Ynp1VaL2 : integer := 1;
    
    signal h_valid_flag, v_valid_flag : std_logic := '1';
    
    begin
    op_int_vaL1 <= Xnm1Ynm1VaL1*CONV_INTEGER(Xnm1Ynm1) + XnYnm1VaL1*CONV_INTEGER(XnYnm1) + Xnp1Ynm1VaL1*CONV_INTEGER(Xnp1Ynm1)
    + Xnm1YnVaL1*CONV_INTEGER(Xnm1Yn) + XnYnVaL1*CONV_INTEGER(XnYn) + Xnp1YnVaL1*CONV_INTEGER(Xnp1Yn)
    + Xnm1Ynp1VaL1*CONV_INTEGER(Xnm1Ynp1) + XnYnp1VaL1*CONV_INTEGER(XnYnp1) + Xnp1Ynp1VaL1*CONV_INTEGER(Xnp1Ynp1);
    
    op_int_vaL2 <= Xnm1Ynm1VaL2*CONV_INTEGER(Xnm1Ynm1) + XnYnm1VaL2*CONV_INTEGER(XnYnm1) + Xnp1Ynm1VaL2*CONV_INTEGER(Xnp1Ynm1)
    + Xnm1YnVaL2*CONV_INTEGER(Xnm1Yn) + XnYnVaL2*CONV_INTEGER(XnYn) + Xnp1YnVaL2*CONV_INTEGER(Xnp1Yn)
    + Xnm1Ynp1VaL2*CONV_INTEGER(Xnm1Ynp1) + XnYnp1VaL2*CONV_INTEGER(XnYnp1) + Xnp1Ynp1VaL2*CONV_INTEGER(Xnp1Ynp1);
    
    op_vaL1 <= CONV_STD_LOGIC_VECTOR(op_int_vaL1, op_vaL1'length);
    op_vaL2 <= CONV_STD_LOGIC_VECTOR(op_int_vaL2, op_vaL2'length);
    
    process(op_vaL1) begin
    if op_vaL1(op_vaL1'left)='1' then
    abs_op_cal_vaL1 <= -op_int_vaL1;
    else
    abs_op_cal_vaL1 <= op_int_vaL1;
    end if;
    end process;
    process(op_vaL2) begin
    if op_vaL2(op_vaL2'left)='1' then
    abs_op_cal_vaL2 <= -op_int_vaL2;
    else
    abs_op_cal_vaL2 <= op_int_vaL2;
    end if;
    end process;
    abs_op_cal_val <= CONV_STD_LOGIC_VECTOR(abs_op_cal_vaL1 + abs_op_cal_vaL2, abs_op_cal_val'length);
    
    
    ydata_out <= x"00" when h_valid_flag='0' or v_valid_flag='0' else
    x"FF" when (abs_op_cal_val(12) or abs_op_cal_val(11) or abs_op_cal_val(10) or abs_op_cal_val(9) or abs_op_cal_val(8))='1'
    else abs_op_cal_val(7 downto 0);
    
    end Behavioral;
    Also, that big addition chain is likely to give pretty lousy performance!
    In general, (w+x)+(y+z) is likely to get better performance then w+x+y+z.
    joris, Dec 4, 2009
    #2
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  3. pplnet

    marina_yassa

    Joined:
    Mar 29, 2013
    Messages:
    1
    entity SA is
    Port ( s1,s2,s3,s4,t1,t2,t3,t4,i1,i2,i3,i4: in std_logic_vector (7 downto 0);
    p1,p2,p3,p4 : out std_logic_vector (7 downto 0) );
    end SA;

    architecture Behavioral of SA is
    type tasks is array(0 to 3) of integer;
    type times is array(0 to 3) of integer;
    type impactR is array(0 to 3) of integer;
    type PU is array(0 to 3) of integer;

    signal my_task : tasks;
    signal my_times : times;
    signal my_impactR : impactR;
    signal my_PU : PU;





    begin

    my_task(0) <= conv_integer(s1);
    my_task(1) <= conv_integer(s2);
    my_task(2) <=conv_integer(s3);
    my_task(3) <= conv_integer(s4);

    my_times(0) <= conv_integer (t1);
    my_times(1) <= conv_integer(t2);
    my_times(2) <= conv_integer(t3);
    my_times(3) <= conv_integer(t4);

    my_impactR(0) <=conv_integer(i1);
    my_impactR(1) <= conv_integer(i2);
    my_impactR(2) <= conv_integer(i3);
    my_impactR(3) <= conv_integer(i4);


    P1: process
    variable minResult : integer;
    variable minSol : integer;
    variable minImpact : integer;
    variable t: integer;
    variable iteration: integer;
    variable Temp : integer ;
    variable len: integer;
    variable e : real ;
    variable x: real;
    variable Imin : integer ;
    variable Jmin: integer;


    begin
    minResult := 75;
    minImpact := 0;
    iteration:= 50;
    Temp := 25;
    len:= 50;
    e := 2.7;
    x:= 1.0;


    for i in 0 to len loop
    if my_times(i) < minResult then
    minResult := my_times(i);
    minSol := my_task(i);
    Imin:= i;
    elsif (e**((my_times(i) - minResult)/ Temp)) > x then
    minResult := my_times(i);
    minSol := my_task(i);
    Imin:= i;
    end if;


    end loop;

    for j in 0 to len loop
    if my_impactR(j) < minImpact then
    minImpact := my_impactR(j);

    Jmin:= j;
    end if;

    end loop;
    p(Jmin) <= conv_std_logic_vector(my_task(Imin),8) ;
    end process;
    end Behavioral;



    and i have these errors

    ERROR:HDLParsers:3312 - "E:/Xilinx Project/trial_SA/SA.vhd" Line 120. Undefined symbol 'p'.
    ERROR:HDLParsers:1209 - "E:/Xilinx Project/trial_SA/SA.vhd" Line 120. p: Undefined symbol (last report in this block)
    ERROR:HDLParsers:3312 - "E:/Xilinx Project/trial_SA/SA.vhd" Line 120. Undefined symbol 'conv_std_logic_vector'.
    ERROR:HDLParsers:1209 - "E:/Xilinx Project/trial_SA/SA.vhd" Line 120. conv_std_logic_vector: Undefined symbol (last report in this block)
    ERROR:HDLParsers:1202 - "E:/Xilinx Project/trial_SA/SA.vhd" Line 121. Redeclaration of symbol P1.



    can anyone help me solve them?
    marina_yassa, Mar 29, 2013
    #3
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