Event counters for simulation only

Discussion in 'VHDL' started by _spot_thegthorpe_extra@ee.ryerson.ca, Jun 26, 2005.

  1. Guest

    Hi,

    I am trying to add internal counters to an entity and have the results output
    at the end of simulation. It is most convenient to do this because there are
    going to be a few million cycles and I cannot examine a waveform to determine
    certain things.

    However, I would like this addition to not be synthesized (because the counters
    would never be used in any meaningful way). Is there any general method to
    accomplish this? Would it be better to just add the counters to the
    synthesize-able design?
    , Jun 26, 2005
    #1
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  2. wrote:

    > However, I would like this addition to not be synthesized (because the counters
    > would never be used in any meaningful way). Is there any general method to
    > accomplish this?


    Use a generic parameter.

    entity my_comp
    generic(
    sim : integer:=0 );
    port(
    ...


    Test inide your component the generic parameter - e.g. with an if-generate:

    if (sim=1) generate
    ....


    If you instantiate your component, override the generic parameter. It is possible to feed
    the generic through several components, that all have to be synthesized. Just assign a
    default value to it, that disables your parts. At the testbench level override it.

    You may even test the parameter inside a process in a normal if-statement. Your synthesis
    tool then should warn you, that a branch can never be reached, but as this is exactly,
    what you want, don't care for the warning.



    Using a generic parameter works with every synthesis tool, but may not be acceptable, if
    your component has to be sold as an IP-core, because such a generic may not be wanted.
    Then there is the option to use synthesis-tool specific switches, like
    -- pragma translate_off
    ....
    -- pragma translate_on
    which is self-explaining. Note, that then your code is not portable.

    Ralf
    Ralf Hildebrandt, Jun 26, 2005
    #2
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  3. wrote:

    > I am trying to add internal counters to an entity and have the results output
    > at the end of simulation. It is most convenient to do this because there are
    > going to be a few million cycles and I cannot examine a waveform to determine
    > certain things.


    Consider bringing the nodes to be counted out to
    a top port -- either with an assignment or using
    modelsim signal-spy. Then the testbench can
    do the counting.

    -- Mike Treseler
    Mike Treseler, Jun 26, 2005
    #3
  4. Guest

    Ralf Hildebrandt <> wrote:
    > Use a generic parameter.


    > entity my_comp
    > generic(
    > sim : integer:=0 );
    > port(
    > ...



    > Test inide your component the generic parameter - e.g. with an if-generate:


    > if (sim=1) generate
    > ...



    > If you instantiate your component, override the generic parameter. It is possible to feed
    > the generic through several components, that all have to be synthesized. Just assign a
    > default value to it, that disables your parts. At the testbench level override it.


    > You may even test the parameter inside a process in a normal if-statement. Your synthesis
    > tool then should warn you, that a branch can never be reached, but as this is exactly,
    > what you want, don't care for the warning.


    This is what I think I will do. I have used generics before, but only in
    generate statements for instantiating components. According to what you are
    saying, the compiler should be smart enough to exclude the unsynthesizeable
    profiling part because it is never activated when doing synthesis.

    > Using a generic parameter works with every synthesis tool, but may not be acceptable, if
    > your component has to be sold as an IP-core, because such a generic may not be wanted.
    > Then there is the option to use synthesis-tool specific switches, like
    > -- pragma translate_off
    > ...
    > -- pragma translate_on
    > which is self-explaining. Note, that then your code is not portable.


    > Ralf


    Thanks for the tips.
    , Jun 27, 2005
    #4
  5. Guest

    Mike Treseler <> wrote:
    > wrote:


    >> I am trying to add internal counters to an entity and have the results output
    >> at the end of simulation. It is most convenient to do this because there are
    >> going to be a few million cycles and I cannot examine a waveform to determine
    >> certain things.


    > Consider bringing the nodes to be counted out to
    > a top port -- either with an assignment or using
    > modelsim signal-spy. Then the testbench can
    > do the counting.


    I thought of doing this, but extra ports and associated circuitry will then be
    included in synthesis won't it? I am trying to let the testbench infer as much
    as it can from the normal ports, but I would prefer not adding more just for
    the purpose of simulation.

    > -- Mike Treseler
    , Jun 27, 2005
    #5
  6. Ajeetha Guest

    Ajeetha, Jun 27, 2005
    #6
  7. wrote:

    > I thought of doing this, but extra ports and associated circuitry will then be
    > included in synthesis won't it?


    Doesn't have to be.
    Signal-spy does not touch the source at all.
    A port testpoint can be commented out or wrapped
    for synthesis.

    -- Mike Treseler
    Mike Treseler, Jun 27, 2005
    #7
  8. Guest

    Ajeetha <> wrote:
    > Hi,
    > With Modelsim's Signal-spy (or equivalents in various others) you
    > don't have to add *any extra port* to your design and still achieve
    > what you intended. I've a simple example that will keep it
    > quasi-simulator indepedent. take a look at:


    > http://www.verificationguild.com/modules.php?name=Downloads&d_op=getit&lid=11


    > HTH
    > Ajeetha
    > http://www.noveldv.com


    Hi,

    Thanks for your tips. I think I will combine package-resident signals (which
    your code uses combined with the tool's extensions) with generics to get add
    profiling code without affecting synthesis. It seems that this is portable and
    would work for what I want to do.

    For future reference for anyone else having similar trouble, see section
    "4.2.16 How to Monitor Signals" in the VHDL FAQ for comp.lang.vhdl.
    Off-topic: is it possible to find the FAQ using an NNTP client (I have to use
    the web page at www.eda.org)?
    , Jun 27, 2005
    #8
  9. Guest

    Ajeetha <> wrote:
    > Hi,
    > With Modelsim's Signal-spy (or equivalents in various others) you
    > don't have to add *any extra port* to your design and still achieve
    > what you intended. I've a simple example that will keep it
    > quasi-simulator indepedent. take a look at:


    > http://www.verificationguild.com/modules.php?name=Downloads&d_op=getit&lid=11


    > HTH
    > Ajeetha
    > http://www.noveldv.com


    Following up:

    I implemented the package-resident signals, but the test bench is just getting
    zero values in the text output. The signals are in fact getting the values
    though: its just that they don't show up in the testsbench's output (all zero
    values). Any idea why this is happening?

    The output from 'ls -v' in vhdlsim (synopsys) indicates that the values are
    being updated (the correct values I expect are there). But those values don't
    show up when I do write(line, value), writeline(output, line). Is there some
    rule about package-resident signals I am missing?
    , Jun 28, 2005
    #9
  10. Guest

    wrote:
    > Ajeetha <> wrote:
    >> Hi,
    >> With Modelsim's Signal-spy (or equivalents in various others) you
    >> don't have to add *any extra port* to your design and still achieve
    >> what you intended. I've a simple example that will keep it
    >> quasi-simulator indepedent. take a look at:


    >> http://www.verificationguild.com/modules.php?name=Downloads&d_op=getit&lid=11


    >> HTH
    >> Ajeetha
    >> http://www.noveldv.com


    > Following up:


    > I implemented the package-resident signals, but the test bench is just getting
    > zero values in the text output. The signals are in fact getting the values
    > though: its just that they don't show up in the testsbench's output (all zero
    > values). Any idea why this is happening?


    > The output from 'ls -v' in vhdlsim (synopsys) indicates that the values are
    > being updated (the correct values I expect are there). But those values don't
    > show up when I do write(line, value), writeline(output, line). Is there some
    > rule about package-resident signals I am missing?


    Sorry for the noise, this was due to a bug in my code.
    , Jun 28, 2005
    #10
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