Events on individual bits of a vector

[Hybr1dz]

I want to test for events on individual bits of a std_logic_vector signal... something like this:

Assume vec is signal vec : std_logic_vector(63 downto 0)...

for i in 63 downto 0 loop
if (vec(i)'event) then
[COLOR="SeaGreen"]--do something[/COLOR]
end if;
end loop;

Unfortunately you can't do this. I get the compile error:

Attribute "event" requires a static signal prefix.

Is there a way to check individual bits of a signal vector for an event?

 

[gzidude]

this might work

Since you need to check 64 bits for events which can occur at any time, you need to generate concurrent hardware to check each one. This code might work:

for i in vec'range generate
	if (vec(i)'event) then
		--do something
	end if;
end generate;

Keep in mind that whatever you put where it says "--do something" will be generated in hardware 64 times.

On second thought, you know what else you can do? To save on hardware you could do this:

--
signal check : bit := '0';
--
check <= vec(63) OR vec(62) OR vec(61) OR vec(60) OR vec(59) OR vec(58) OR vec(57) OR vec(56) OR vec(55) OR vec(54) OR 
         vec(53) OR vec(52) OR vec(51) OR vec(50) OR vec(49) OR vec(48) OR vec(47) OR vec(46) OR vec(45) OR vec(44) OR 
         vec(43) OR vec(42) OR vec(41) OR vec(40) OR vec(39) OR vec(38) OR vec(37) OR vec(36) OR vec(35) OR vec(34) OR 
         vec(33) OR vec(32) OR vec(31) OR vec(30) OR vec(29) OR vec(28) OR vec(27) OR vec(26) OR vec(25) OR vec(24) OR 
         vec(23) OR vec(22) OR vec(21) OR vec(20) OR vec(19) OR vec(18) OR vec(17) OR vec(16) OR vec(15) OR vec(14) OR 
         vec(13) OR vec(12) OR vec(11) OR vec(10) OR vec(9)  OR vec(8)  OR vec(7)  OR vec(6)  OR vec(5)  OR vec(4)  OR 
         vec(3)  OR vec(2)  OR vec(1)  OR vec(0);

if (check 'event) then
	--do something
end if;

..that's what I would do. It'll save a lot more hardware space. Your code is uglier, but you get better results

 

[Hybr1dz]

hmmm... interesting. I didn't know you can use generate in that manner (I only used it to for entities).

But are you sure that works? I just tried it and I get an "Illegal concurrent statement" error. I was supposed to check for events in my testbench but I decided to use your code inside my entity (where I also use several generate statements) and it gives me that error.

 

[gzidude]

Sorry about that. I just modified my previous post. Perhaps that'll help. I've been away from VHDL for a while and have gotten pretty rusty.

 

[Hybr1dz]

Thanks for your input! I really appreciate it.

Unfortunately, there was something I forgot to mention. That "do something" actually needs to know which bit has that event. To do something like this:

if (vec(i)'event) then
       another_vec(i) := '1';
else
       another_vec(i) := '0';
end if;

And actually, instead of having that vec(63) OR .... OR vec(0) concurrent signal assignment. You actually can do the following:

if(vec'event) then
     --do something
end if;

Which should do the same thing.

vec'event compiles. vec(i)'event does not. So my problem is that I actually need to know which bit in the vector has an event.

Thanks again for your efforts though!

 

[gzidude]

Dang! I really have been away.

 

[Hybr1dz]

I have a basic solution going... not really elegant. Basically I have another variable that stores the previous values of 'vec' and XORs them with current values of vec.

-- assume variable prev_vec_vals : std_logic_vector (63 downto 0) := (others => '0');
-- assume variable events : boolean := (others => false);
-- assume signal vec : std_logic_vector (63 downto 0);

for i in vec'range loop
     if ( vec(i) xor prev_vec_vals(i) = '1') then
          events(i) := true;
          prev_vec_vals(i) := vec(i);
     end if;
end loop;

Then I would examine the events vector to see which bits had an event. If I were to use this in a looping testbench, then that events vector must be cleared before each iteration.

It seems to be working fine right now. Perhaps someone who ran into my problem could find this useful.