Extension of submission deadline for EDPS 2006: March 05, 2006

B

b_kapoor

Dear Friends,

I am writing to encourage you all to submit relevant work to the 2006
Workshop on Electronic Design Processes in Monterey immediately after
ISPD. The deadline for submission has been extended to March 05, 2006.

EDP is a small but IMO very good workshop. Invited speakers this year
include Kurt Keutzer, Jason Cong, Jan Rabaey, Rajesh Gupta, Gary Smith,
and Steve Longoria.

While we are interested in all aspects of the design process, a major
focus this year is "Design Above RTL". Supporting SuperSize Designs and
Programmable Platforms are also of interest.

Since EDP is a workshop which encourages free exchange of new ideas,
extended abstracts, position papers, and reports on works in progress
are very suitable.

Below is the CFP. Please do not hesitate to contact me or Bhanu Kapoor
if you have any questions.

Regards,
--John

----------------------


CALL FOR PAPERS - EDP 2006
Electronic Design Processes 2006
April 13&14, 2006
Monterey Beach Hotel, Monterey, California
http://www.eda.org/edps/edps06


The Electronic Design Processes (EDP) Workshop provides a forum for a
cross-section of the design community to discuss state-of-the-art
electronic design processes and CAD methodologies. As the requirements
and complexities of electronic design increase, past ad-hoc approaches
to design processes are proving inadequate. The workshop focuses on the
improvement of the overall design process, rather than on the functions
of the individual tools themselves. The core audience of EDP consists
of CAD system integrators and methodologists, academic researchers, and
design team managers.

Themes in 2006: Design Above RTL, Supporting "Super-Sized"
Designs and Impact of Programmable Devices and Platforms

We solicit papers and proposals for special/panel sessions that shed
light on the methodologies used for real current and future chip and
system designs. Topics include but are not limited to:
Best practices and experiences
Domain-specific methodologies: SOC, analog / mixed-signal, RF
Metrics
Cost, time-to-market, productivity
Flow integration/optimization
Scaling and migration
Scaling to "Super Size"
Co-evolution of methodology and process technology
Human issues
Large/distributed design teams
Training and education
Manufacturing integration
Process/device characterization, modeling
Domain-specific methodologies
Functional verification
RTL-down implementation
HW/SW co-design
IP reuse
Key trends
Future methodology needs and concepts
Impact of design-manufacturing interface
Process advances and multi-technology integration
New tool/algorithms
Interoperability
Impact of the web, licensing models, and platforms

PAPER SUBMISSION
Unpublished workshop notes will be distributed to attendees. All papers
must be submitted electronically through the website or by email to
(e-mail address removed). Authors should submit full-length, original and
unpublished papers (maximum 20 pages in single-column double spaced
format, or 6 pages in double-column conference proceedings format)
along with author contact information. Proposals for special and
panel sessions may also be submitted; a 1-page description along with
organizer contact information is required.

IMPORTANT DATES

Submission Deadline March 05, 2006
On-site registration April 12, 2006

ORGANIZATION
General Chair: John Lillis (UIC)
Program Chair: Bhanu Kapoor (Atrenta)
Publications Chair: Kumar Venkatramani (SoftJin)
WebMaster: Steve Grout
Sponsors: IEEE DATC and CS.

Program Committee:

Michael Bohm (AccelChip)
Elaheh Bozorgzadeh (UCI)
Juan-Antonio Carballo (IBM)
Arpana Dey (Cadence)
Steve Grout
Bill Halpin (Synplicity)
Dwight Hill (Synopsys)
Takahide Inoue (STARC)
Andrew B. Kahng (UCSD)
Bhanu Kapoor (Atrenta)
John Lillis (UIC)
José Augusto Lima (Univ. Of Minho)
Patrick Madden (Binghamton)
Gabe Moretti (EDN)
Naresh Sehgal (Intel)
Sandeep Shukla (Virginia Tech)
Gary Smith (Gartner/Dataquest)
Kumar Venkatramani (SoftJin)
 

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