External names vhdl2008

[Pierre]

I found that an alias could not not be used to shorten an external
names in VHDL 2008.
Instead I have to use a signal instead.See the small example below.
Any better idea ?

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY inv IS

PORT (
i : IN std_logic;
zn : BUFFER std_logic
);

END ENTITY inv;

ARCHITECTURE rtl OF inv IS
SIGNAL zb : std_logic;
BEGIN

zb <= NOT i;
zn <= NOT i;

END ARCHITECTURE rtl;
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hinv IS

PORT (
i : IN std_logic;
zn : BUFFER std_logic
);

END ENTITY hinv;

ARCHITECTURE str OF hinv IS

COMPONENT inv IS

PORT (
i : IN std_logic;
zn : BUFFER std_logic
);

END COMPONENT inv;

alias xx is <<signal .u1.zb: std_logic>>;

BEGIN
u1: inv
PORT MAP (
i => i,
zn => zn
);

END ARCHITECTURE str;
--
ARCHITECTURE str1 OF hinv IS

COMPONENT inv IS

PORT (
i : IN std_logic;
zn : BUFFER std_logic
);

END COMPONENT inv;
SIGNAL xx : std_logic;
BEGIN
xx <= <<signal .u1.zb: std_logic>>;
u1: inv
PORT MAP (
i => i,
zn => zn
);

END ARCHITECTURE str1;

 

[JimLewis]

Pierre,
An alias to an external name has the class of the object
you have aliased to, so you first example should work.
Make sure to submit it as a bug to your vendor - even
if they already know about it, this helps them understand
that they need to prioritize it.

Your work around looks as good as any until your
vendor gets the VHDL-2008 feature working.

Best,
Jim

 

[Pierre]

Pierre,
An alias to an external name has the class of the object
you have aliased to, so you first example should work.
Make sure to submit it as a bug to your vendor - even
if they already know about it, this helps them understand
that they need to prioritize it.

Your work around looks as good as any until your
vendor gets the VHDL-2008 feature working.

Best,
Jim

Hi Jim,
Thanks for your answer.
I already submitted the issue.The test case was a bit more
complicated.
I got the following answer :


”You are trying to use an external name before the object exists. In
this case the alias to /tb/u2/zb occurs before the instance u2 is
elaborated because the alias occurs in the architecture declaration
region which is elaborated before any statements are done”.

When an external name is evaluated during elaboration, the target
object of the external name must already have been elaborated. A
common error is to declare, in a declarative region in which a design
hierarchy that will contain the target object of an external name, an
alias declaration that denotes the object denoted by the external
name. In the case of a relative pathname, this can be detected at
compile time; other cases such as an absolute path or a path that
contains up-scope reference(s) cannot be detected until run time.

# [DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names]

# [DOC: IEEE Std 1076-2008 VHDL LRM - 14.4.1 Elaboration of
declarative part, General]

The alias is my opinion much better.And I dont see what would be more
difficult in the implementation between the workaround and the alias.

 

[JimLewis]

Pierre,
They are right about that. VHDL elaborates the design in the order
that items occur. So technically neither of the testcases you showed
should have worked.

It really depends on how you plan to use the signal XX. In your
testbench, you can declare the alias in a process or block statement
declarative region that follow the design instance.


I expect to use this feature in the stimulus generation portion of my
testbench. I do stimulus generation in a separate entity/
architecture. As a result, the only thing I need to do is make sure
the entity that is going to do the access is elaborated last.


Best,
Jim