Failure: (vsim-3807) Types do not match between component and entity for port "out1".

Discussion in 'VHDL' started by deesaid, Dec 3, 2011.

  1. deesaid

    deesaid

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    Dec 3, 2011
    Messages:
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    Hi, i got Failure: (vsim-3807) Types do not match between component and entity for port "out1". I got also failure for port out2 and so on.

    When i check component in haar_tb.vhd : testbench file is same with entity in haar.vhd. Can I know what the solution for this problem.
    deesaid, Dec 3, 2011
    #1
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  2. deesaid

    deesaid

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    i got the error message when i click on EDA Gate Level simulation.
    deesaid, Dec 3, 2011
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  3. deesaid

    joris

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    you'll have to post the relevant code for anyone to be able to help.
    Double check inputs and outputs, as well as setting correct 'generic' values
    joris, Dec 5, 2011
    #3
  4. deesaid

    deesaid

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    Dec 3, 2011
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    Before that,i'm a beginner in vhdl code & fpga (altera), i want to ask question
    my program:compilation and RTL simulation is success,but gate level simulation is not success, Is it effect when running the program in fpga?

    For your information,RTL and gate level simulation in model sim
    deesaid, Dec 16, 2011
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