Fake vcc and gnd

Discussion in 'VHDL' started by aushitha, Apr 23, 2006.

  1. aushitha

    aushitha Guest

    If your code generates a fake vcc while synthesis,how do you overcome
    it?In behaviourial modelling how can you know whether your code is
    generating a fake vcc or not?Please let me know asap if anybody faced
    this problem and overcame it.
     
    aushitha, Apr 23, 2006
    #1
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  2. Mike Treseler, Apr 23, 2006
    #2
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  3. aushitha

    aushitha Guest

    If your code generates a fake vcc while synthesis,how do you overcome
    it?In behaviourial modelling how can you know whether your code is
    generating a fake vcc or not?Please let me know asap if anybody faced
    this problem and overcame it.I am using Mentor Graphics - Leonardo
    Spectrum,TSMC 0.35u tech.
     
    aushitha, Apr 24, 2006
    #3
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