False Path Definition

Discussion in 'VHDL' started by Ardni, Jun 5, 2009.

  1. Ardni

    Ardni

    Joined:
    Jul 8, 2008
    Messages:
    23
    Hi,
    After doing quite a bit of research on false paths, I still do not have the concept clear in my head. Can somebody advise if the below example would be considered a false path?

    Process 1:
    If rising edge (66MHz_clk) then
    alarm_signal <= '1'
    end

    Process 2:
    If rising edge (10MHz_clk) then
    if alarm_signal = '1' then
    do something
    end


    I have something similar in a current design and I am recieving timing warnings. I later set the paths between both clocks (in both directions) as a false path and it has cleared up any timing issues.

    Is this ok to do?

    If possible, can someone please describe when and where it is ok to make a false path, e.g. what the circumstances must be.


    Thanks very much for any advise.
    Ardni, Jun 5, 2009
    #1
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