Fanout Delay?

Discussion in 'VHDL' started by Jim, Nov 2, 2004.

  1. Jim

    Jim Guest

    Hello

    Here is part of the timing constraints output for my design:


    Timing constraint: Default OFFSET IN BEFORE for Clock 'mst_clk'
    Offset: 9.162ns (Levels of Logic = 2)
    Source: mst_rst
    Destination: idsel_ff_Mtrien_q
    Destination Clock: mst_clk rising

    Data Path: mst_rst to idsel_ff_Mtrien_q
    Gate Net
    Cell:in->out fanout Delay Delay Logical Name (Net Name)
    ---------------------------------------- ------------
    IBUF:I->O 13 0.797 2.000 mst_rst_IBUF (mst_rst_IBUF)
    LUT1:I0->O 89 0.468 5.320 I_INV_mst_rst (N493)
    FDP:pRE 0.577 idsel_ff_Mtrien_q
    ----------------------------------------
    Total 9.162ns (1.842ns logic, 7.320ns route)
    (20.1% logic, 79.9% route)


    mst_rst is an asychronus reset for the whole system. And idsel_ff is a flip
    flop, which has a asynchronus reset and a synchronus output enable.

    If the reset is asynchrnous then how come it is associated with the rising
    edge of the clock? And is the reason for the large time of 9.162ns due to
    the high fanout?

    Are there any techniques for dealing with fanout times (other than place and
    route)?

    TIA
     
    Jim, Nov 2, 2004
    #1
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  2. Jim

    rickman Guest

    Jim wrote:
    >
    > Hello
    >
    > Here is part of the timing constraints output for my design:
    >
    > Timing constraint: Default OFFSET IN BEFORE for Clock 'mst_clk'
    > Offset: 9.162ns (Levels of Logic = 2)
    > Source: mst_rst
    > Destination: idsel_ff_Mtrien_q
    > Destination Clock: mst_clk rising
    >
    > Data Path: mst_rst to idsel_ff_Mtrien_q
    > Gate Net
    > Cell:in->out fanout Delay Delay Logical Name (Net Name)
    > ---------------------------------------- ------------
    > IBUF:I->O 13 0.797 2.000 mst_rst_IBUF (mst_rst_IBUF)
    > LUT1:I0->O 89 0.468 5.320 I_INV_mst_rst (N493)
    > FDP:pRE 0.577 idsel_ff_Mtrien_q
    > ----------------------------------------
    > Total 9.162ns (1.842ns logic, 7.320ns route)
    > (20.1% logic, 79.9% route)
    >
    > mst_rst is an asychronus reset for the whole system. And idsel_ff is a flip
    > flop, which has a asynchronus reset and a synchronus output enable.
    >
    > If the reset is asynchrnous then how come it is associated with the rising
    > edge of the clock? And is the reason for the large time of 9.162ns due to
    > the high fanout?
    >
    > Are there any techniques for dealing with fanout times (other than place and
    > route)?


    I am not sure what you are looking for. The info above is telling you
    the amount of setup time you need for the reset signal relative to the
    rising edge of the clock on the FF. It does not include the delay for
    the clock from pin to FF which will reduce your extermal pin to pin
    setup time (so you need to know the min clock routing delay, not the
    max; or treat this as zero). The async reset must be released some
    point prior to a clock edge to be sure the FF will then operate
    correctly. If you don't care about all the FFs being released on the
    same clock edge, then this time is not useful.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Nov 3, 2004
    #2
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