Fatal Error in Modelsim when loading a design

Discussion in 'VHDL' started by aim9x, Apr 10, 2009.

  1. aim9x

    aim9x

    Joined:
    Jun 18, 2008
    Messages:
    1
    I've met with the following error when try to load a design in Modelsim.

    ** Fatal: (SIGSEGV) Bad handle or reference

    I have used Modelsim for one year and this is the first time I have this error. The design is quite simple, which is just a timer block. And there's no errors or warnings during compilation.

    Below is the code of my design:
    -----------------------------------------------------------------------------
    -- Entity: timer_block
    -- File: timer_block.vhd
    -- Generics:
    -- name type
    -- stall_width integer
    -- elapse_width integer
    --
    -- Inputs:
    -- clk
    -- rstn
    -- rst_timer0
    -- rst_timer2
    -- rst_timer4
    -- reload_timer1
    -- reload_timer3
    -- relaod_value1
    -- reload_value3
    --
    -- Outputs:
    -- unf_timer1
    -- unf_timer3
    -- ovf_timer0
    -- ovf_timer2
    -- ovf_timer4
    -- timer0
    -- timer2
    -- timer4
    --
    -- Rev. History
    -----------------------------------------------------------------------------

    library IEEE;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all;

    entity timer_block is
    generic(
    stall_width : integer := 8;
    elapse_width : integer := 32
    );
    port (
    -- Inputs:
    clk : in std_logic;
    rstn : in std_logic;
    rst_timer0 : in std_logic;
    rst_timer2 : in std_logic;
    rst_timer4 : in std_logic;

    reload_timer1 : in std_logic;
    reload_timer3 : in std_logic;

    reload_value1 : in std_logic_vector(stall_width - 1 downto 0);
    reload_value3 : in std_logic_vector(stall_width - 1 downto 0);

    -- Outputs:
    unf_timer1 : out std_logic;
    unf_timer3 : out std_logic;

    ovf_timer0 : out std_logic;
    ovf_timer2 : out std_logic;
    ovf_timer4 : out std_logic;

    time0 : out std_logic_vector(stall_width - 1 downto 0);
    time2 : out std_logic_vector(stall_width - 1 downto 0);
    time4 : out std_logic_vector(elapse_width - 1 downto 0)
    );
    end entity;

    architecture rtl of timer_block is
    constant OVF_INC : std_logic_vector(stall_width - 1 downto 0) := (others => '1');
    constant UNF_DEC : std_logic_vector(stall_width - 1 downto 0) := (others => '0');
    constant OVF_ELA : std_logic_vector(elapse_width - 1 downto 0) := (others => '1');

    type inc_timer_type is record
    count : std_logic_vector(stall_width - 1 downto 0);
    ovf : std_logic;
    end record;

    type dec_timer_type is record
    count : std_logic_vector(stall_width - 1 downto 0);
    -- unf : std_logic;
    end record;

    type elap_timer_type is record
    count : std_logic_vector(elapse_width - 1 downto 0);
    ovf : std_logic;
    end record;

    type timer_block_type is record
    de_inc : inc_timer_type;
    de_dec : dec_timer_type;
    mem_inc : inc_timer_type;
    mem_dec : dec_timer_type;
    elap_inc : elap_timer_type;
    end record;

    signal tb : timer_block_type;

    begin

    -- Each timer manages itself;

    tm0: process (clk, rstn, rst_timer0, tb.de_inc) is
    begin
    if rising_edge(clk) then
    if (rstn = '0') or (rst_timer0 = '1') then
    tb.de_inc.count <= (others => '0');
    tb.de_inc.ovf <= '0';
    else
    tb.de_inc.count <= std_logic_vector(unsigned(tb.de_inc.count) + 1);
    if tb.de_inc.count = OVF_INC then
    tb.de_inc.ovf <= '1';
    end if;
    end if;
    end if;
    end process;

    time0 <= tb.de_inc.count;
    ovf_timer0 <= tb.de_inc.ovf;

    tm1: process(clk, rstn, reload_timer1, reload_value1, tb.de_dec) is
    begin
    if rising_edge(clk) then
    if rstn = '0' then
    tb.de_dec.count <= (others => '0');
    elsif reload_timer1 = '1' then
    tb.de_dec.count <= reload_value1;
    else
    tb.de_dec.count <= std_logic_vector(unsigned(tb.de_dec.count) - 1);
    end if;
    end if;
    end process;

    unf_timer1 <= '1' when tb.de_dec.count = UNF_DEC else '0';

    tm2: process (clk, rstn, rst_timer2, tb.mem_inc) is
    begin
    if rising_edge(clk) then
    if (rstn = '0') or (rst_timer2 = '1') then
    tb.mem_inc.count <= (others => '0');
    tb.mem_inc.ovf <= '0';
    else
    tb.mem_inc.count <= std_logic_vector(unsigned(tb.mem_inc.count) + 1);
    if tb.mem_inc.count = OVF_INC then
    tb.mem_inc.ovf <= '1';
    end if;
    end if;
    end if;
    end process;

    time2 <= tb.mem_inc.count;
    ovf_timer2 <= tb.mem_inc.ovf;

    tm3: process(clk, rstn, reload_timer3, reload_value3, tb.mem_dec) is
    begin
    if rising_edge(clk) then
    if rstn = '0' then
    tb.mem_dec.count <= (others => '0');
    elsif reload_timer1 = '1' then
    tb.mem_dec.count <= reload_value3;
    else
    tb.mem_dec.count <= std_logic_vector(unsigned(tb.mem_dec.count) - 1);
    end if;
    end if;
    end process;

    unf_timer3 <= '1' when tb.mem_dec.count = UNF_DEC else '0';

    tm4: process (clk, rstn, rst_timer4, tb.elap_inc) is
    begin
    if rising_edge(clk) then
    if (rstn = '0') or (rst_timer4 = '1') then
    tb.elap_inc.count <= (others => '0');
    tb.elap_inc.ovf <= '0';
    else
    tb.elap_inc.count <= std_logic_vector(unsigned(tb.elap_inc.count) + 1);
    if tb.elap_inc.count = OVF_ELA then
    tb.elap_inc.ovf <= '1';
    end if;
    end if;
    end if;
    end process;

    time4 <= tb.elap_inc.count;
    ovf_timer4 <= tb.elap_inc.ovf;
    end architecture;
     
    aim9x, Apr 10, 2009
    #1
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