FF with CE doesn't synthesize correctly by XST?

Discussion in 'VHDL' started by MM, Sep 26, 2003.

  1. MM

    MM Guest

    Hi all,

    I want the code below to synthesize as a FF with a sync reset and CE,
    however XST does something quite different (target technology is Virtex II).
    It routes my clk_ena signal to the REV pin and ties D and CE to VCC. The
    sync_reset is recognized OK and gets routed correctly to the SR pin. I
    realize that if I had a "regular" input signal instead of '1' under the
    clock enable statement it would have worked fine, but what should I do if I
    need to tie it to VCC?

    process(clk)
    begin
    if rising_edge (clk) then
    if sync_reset='1' then
    outf <= '0';
    elsif clk_ena='1' then
    outf <= '1';
    end if;
    end if;
    end process;

    Thanks,
    /Mikhail
     
    MM, Sep 26, 2003
    #1
    1. Advertising

  2. MM wrote:
    > Hi all,
    >
    > I want the code below to synthesize as a FF with a sync reset and CE,
    > however XST does something quite different (target technology is Virtex II).
    > It routes my clk_ena signal to the REV pin and ties D and CE to VCC.


    XST is just doing its job, making a valid netlist per your description.
    A synth will often do unexpected things, but it will work just fine.

    > The
    > sync_reset is recognized OK and gets routed correctly to the SR pin. I
    > realize that if I had a "regular" input signal instead of '1' under the
    > clock enable statement it would have worked fine,


    Both are "fine".
    You write the description, the synth makes the netlist.

    -- Mike Treseler


    -- makes an fdre module on Virtex:
    library ieee;
    use ieee.std_logic_1164.all;

    entity sreset_ce is
    port (
    clk : in std_ulogic;
    clk_ena : in std_ulogic;
    sync_reset : in std_ulogic;
    inf : in std_ulogic;
    outf : out std_ulogic);

    end entity sreset_ce;

    architecture synth of sreset_ce is
    begin
    process(clk) is
    begin
    if rising_edge (clk) then
    if sync_reset = '1' then
    outf <= '0';
    elsif clk_ena = '1' then
    outf <= inf;
    end if;
    end if;
    end process;
    end architecture synth;
     
    Mike Treseler, Sep 26, 2003
    #2
    1. Advertising

  3. Mikhail,
    Your last statement suggests a solution.
    Have you tried creating signal and assigning that to one outside of the process?

    I this may (or may not) work.

    If you absolutely want some particular interconnect configuration of a Xilinx
    Basic Element you can always instantiate any component in the the unisim library

    (unisim_VCOMP.vhd) FDRE in this case

    I'll also just mention XST implementation is logically correct even if it wasn't
    what
    you wanted.

    Chris



    MM wrote:

    > Hi all,
    >
    > I want the code below to synthesize as a FF with a sync reset and CE,
    > however XST does something quite different (target technology is Virtex II).
    > It routes my clk_ena signal to the REV pin and ties D and CE to VCC. The
    > sync_reset is recognized OK and gets routed correctly to the SR pin. I
    > realize that if I had a "regular" input signal instead of '1' under the
    > clock enable statement it would have worked fine, but what should I do if I
    > need to tie it to VCC?
    >
    > process(clk)
    > begin
    > if rising_edge (clk) then
    > if sync_reset='1' then
    > outf <= '0';
    > elsif clk_ena='1' then
    > outf <= '1';
    > end if;
    > end if;
    > end process;
    >
    > Thanks,
    > /Mikhail
     
    Chris Ebeling, Sep 26, 2003
    #3
  4. MM

    MM Guest

    "Mike Treseler" <> wrote in message
    news:...
    > MM wrote:
    > > Hi all,
    > >
    > > I want the code below to synthesize as a FF with a sync reset and CE,
    > > however XST does something quite different (target technology is Virtex

    II).
    > > It routes my clk_ena signal to the REV pin and ties D and CE to VCC.

    >
    > XST is just doing its job, making a valid netlist per your description.
    > A synth will often do unexpected things, but it will work just fine.


    I don't think the netlist is valid. With D and CE both tied to VCC the flop
    reverts to '1' on every clock regardless of my clk_ena signal. This is a
    part of a bigger design that used to work on Spartan II. I only found the
    problem when I moved it to Virtex II.... Any other ideas?

    Thanks,
    /Mikhail
     
    MM, Sep 26, 2003
    #4
  5. MM wrote:

    > I don't think the netlist is valid. With D and CE both tied to VCC the flop
    > reverts to '1' on every clock regardless of my clk_ena signal.


    Your description says outf is low for reset, high otherwise.
    The only way to get a low with that description
    is to reset and immediately disble the clock.

    -- Mike Treseler
     
    Mike Treseler, Sep 26, 2003
    #5
  6. MM

    MM Guest

    OK, so how should I describe a D flip-flop with a synchronous reset and a
    clock enable with the D input tied to VCC?

    /Mikhail


    "Mike Treseler" <> wrote in message
    news:...
    > MM wrote:
    >
    > > I don't think the netlist is valid. With D and CE both tied to VCC the

    flop
    > > reverts to '1' on every clock regardless of my clk_ena signal.

    >
    > Your description says outf is low for reset, high otherwise.
    > The only way to get a low with that description
    > is to reset and immediately disble the clock.
    >
    > -- Mike Treseler
    >
     
    MM, Sep 26, 2003
    #6
  7. MM

    MM Guest

    "Chris Ebeling" <> wrote in message
    news:...
    > Mikhail,
    > Your last statement suggests a solution.
    > Have you tried creating signal and assigning that to one outside of the

    process?
    >
    > I this may (or may not) work.


    Tried, it doesn't work.

    > If you absolutely want some particular interconnect configuration of a

    Xilinx
    > Basic Element you can always instantiate any component in the the unisim

    library
    >
    > (unisim_VCOMP.vhd) FDRE in this case


    I would like to avoid this.

    > I'll also just mention XST implementation is logically correct even if it

    wasn't
    > what
    > you wanted.


    So, is there a way to describe what I want in VHDL so that XST will
    understand it?

    /Mikhail
     
    MM, Sep 26, 2003
    #7
  8. MM

    Vinh Pham Guest

    You could try to break your process into two seperate ones. Sometimes
    "rewording" your code has an effect on the synthesizer:

    process(clk,inf)
    begin
    if rising_edge(clk) then
    outf <= inf;
    end if;
    end process;

    process(sync_reset,clk_ena,outf)
    begin
    if sync_reset = '1' then
    inf <= '0';
    elsif clk_ena = '1' then
    inf <= '1';
    else
    inf <= outf;
    end if;
    end process;

    If you get desperate, you can manually instantiate a FF. It won't be as
    portable, of course.

    From what code you have shown us, I can't see why the XST is doing what it's
    doing, unless the logic generating sync_reset and clk_ena is somehow causing
    you problems. You could run a quick experiment and synthesize only that
    piece of FF code, in your post, making sync_reset and clk_ena into ports, to
    see what the synthesizer does.

    Best of luck.


    Regards,
    Vinh
     
    Vinh Pham, Sep 26, 2003
    #8
  9. MM

    MM Guest

    I've just tried synthesizing the same code for Spartan II. The result is
    similar in terms of using REV pin, however in this case the D and CE are
    (correctly in my opinion) tied to GND!

    So, at the very least the synthesis results are not consistent and I still
    think the netlist for Virtex II is not valid.

    /Mikhail
     
    MM, Sep 26, 2003
    #9
  10. MM

    Vinh Pham Guest

    I agree with Mikhail. The real problem is CE being connected to VCC. If it
    was connected to GND (doesn't matter what D is connected to), things would
    be fine.
     
    Vinh Pham, Sep 26, 2003
    #10
  11. MM

    MM Guest

    Thanks, Vinh. Just to clarify, I am using ISE 5.2.03i. Can anyone with 6.1
    check this out? Here is the code:

    entity weirdff is
    Port ( clk : in std_logic;
    clk_ena : in std_logic;
    sync_reset : in std_logic;
    outf : out std_logic);
    end weirdff;

    architecture rtl of weirdff is

    begin

    process(clk)
    begin
    if rising_edge (clk) then
    if sync_reset ='1' then
    outf <= '0';
    elsif clk_ena ='1' then
    outf <= '1';
    end if;
    end if;
    end process;

    end rtl;

    Synthesize it for Spartan II and Virtex II and see the results in the FPGA
    Editor....


    /Mikhail


    "Vinh Pham" <> wrote in message
    news:3S_cb.5816$...
    > I agree with Mikhail. The real problem is CE being connected to VCC. If

    it
    > was connected to GND (doesn't matter what D is connected to), things would
    > be fine.
    >
    >
     
    MM, Sep 26, 2003
    #11
  12. MM

    MM Guest

    Folks,

    It seems that I owe Xilinx an apology... I overlooked little muxes with
    invertors enabled at the CE and D inputs for Virtex II architecture. So, the
    CE and D are not really tied to VCC and I have nobody to blame for my
    problem:(

    /Mikhail
     
    MM, Sep 26, 2003
    #12
  13. MM

    Andy Peters Guest

    "MM" <> wrote in message news:<bl1i00$76rai$-berlin.de>...
    > Hi all,
    >
    > I want the code below to synthesize as a FF with a sync reset and CE,
    > however XST does something quite different (target technology is Virtex II).
    > It routes my clk_ena signal to the REV pin and ties D and CE to VCC. The
    > sync_reset is recognized OK and gets routed correctly to the SR pin. I
    > realize that if I had a "regular" input signal instead of '1' under the
    > clock enable statement it would have worked fine, but what should I do if I
    > need to tie it to VCC?
    >
    > process(clk)
    > begin
    > if rising_edge (clk) then
    > if sync_reset='1' then
    > outf <= '0';
    > elsif clk_ena='1' then
    > outf <= '1';
    > end if;
    > end if;
    > end process;


    This is interesting. Carefully re-read the data sheet. Page 12 of
    the "Virtex II Platform FPGAs: Detailed Description" data sheet says
    that, "if SR is used, the BY input is used to force the storage
    element into the opposite state."

    In your case, SR is used as the sync reset. And you're not using
    clk_ena as a clock enable, really, you're just using it as a
    synchronous set, which the tool correctly recognizes and puts on REV
    (through BY).

    However, the odd thing is that both CE and D are set high in the flop,
    which should result in the output of the flop _always_ high (except
    when sync_reset) asserted. What are your pre- and post-route
    simulations telling you?

    =a
     
    Andy Peters, Sep 26, 2003
    #13
  14. MM

    MM Guest

    > However, the odd thing is that both CE and D are set high in the flop,
    > which should result in the output of the flop _always_ high (except
    > when sync_reset) asserted. What are your pre- and post-route
    > simulations telling you?


    I will repeat my apology to Xilinx and that I was wrong as I overlooked
    little muxes with invertors enabled at the CE and D inputs for Virtex II
    architecture.

    /Mikhail
     
    MM, Sep 26, 2003
    #14
  15. MM

    Vinh Pham Guest

    > It seems that I owe Xilinx an apology... I overlooked little muxes with
    > invertors enabled at the CE and D inputs for Virtex II architecture. So,

    the
    > CE and D are not really tied to VCC and I have nobody to blame for my
    > problem:(


    Heh heh honest mistake. It's very easy for humans to overlook small
    details. Or sometimes we spend so much time staring at a problem, we can't
    see the "obvious." Finally the mystery is solved!
     
    Vinh Pham, Sep 26, 2003
    #15
  16. What about the case where sync_reset=0 and clk_ena=0? Your code
    doesn't describe the desired behavior for this case.

    Jake


    "MM" <> wrote in message news:<bl1i00$76rai$-berlin.de>...
    > process(clk)
    > begin
    > if rising_edge (clk) then
    > if sync_reset='1' then
    > outf <= '0';
    > elsif clk_ena='1' then
    > outf <= '1';
    > end if;
    > end if;
    > end process;
    >
    > Thanks,
    > /Mikhail
     
    Jake Janovetz, Sep 26, 2003
    #16
  17. MM

    MM Guest

    "Jake Janovetz" <> wrote in message
    news:...
    > What about the case where sync_reset=0 and clk_ena=0? Your code
    > doesn't describe the desired behavior for this case.


    Compare to the standard DFF description below. It is not required to
    explicitly specify what to do when CE='0'...

    process(clk)
    begin
    if rising_edge (CLK) then
    if CE='1' then
    Q <= D;
    end if;
    end if;
    end process;

    /Mikhail


    >
    > "MM" <> wrote in message

    news:<bl1i00$76rai$-berlin.de>...
    > > process(clk)
    > > begin
    > > if rising_edge (clk) then
    > > if sync_reset='1' then
    > > outf <= '0';
    > > elsif clk_ena='1' then
    > > outf <= '1';
    > > end if;
    > > end if;
    > > end process;
    > >
    > > Thanks,
    > > /Mikhail
     
    MM, Sep 28, 2003
    #17
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Kload

    What does + synthesize to?

    Kload, Sep 1, 2003, in forum: VHDL
    Replies:
    1
    Views:
    525
    Ralf Hildebrandt
    Sep 1, 2003
  2. Replies:
    4
    Views:
    1,011
    David Bishop
    Jun 16, 2005
  3. Tim Verstraete
    Replies:
    1
    Views:
    570
    Mike Treseler
    Sep 12, 2005
  4. Colin Paul Gloster

    Re: infinite synthesize time

    Colin Paul Gloster, Feb 14, 2006, in forum: VHDL
    Replies:
    4
    Views:
    702
    Mike Treseler
    Feb 23, 2006
  5. Ben Jones

    Re: infinite synthesize time

    Ben Jones, Feb 15, 2006, in forum: VHDL
    Replies:
    0
    Views:
    501
    Ben Jones
    Feb 15, 2006
Loading...

Share This Page