FFT in VHDL (or Verilog) Tutorial

Discussion in 'VHDL' started by Student (confused), Nov 14, 2006.

  1. Hello,

    Can someone point me to simple implementation of FFT in VHDL(or
    Verilog) with testbench and good step-by-step description. I have
    implementation from Xilinx (which I will eventually use for hardware
    implementation), but I find it rather confusing (lack of vhdl
    experience). Algorithm used, # of points, Radix#, bit precision do not
    matter, as I'm looking for tutorial-like implementation.
    The best example of what I'm looking for is (found using google)
    http://www.opencores.org/projects.cgi/web/cf_fft/overview
    http://www.opencores.org/cvsweb.shtml/fft/

    Thanks.
     
    Student (confused), Nov 14, 2006
    #1
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  2. Tell me from which university and departmant you are, and also your
    name, then I can answer your question. Of course for free ;-)

    Student (confused) schrieb:

    > Hello,
    >
    > Can someone point me to simple implementation of FFT in VHDL(or
    > Verilog) with testbench and good step-by-step description. I have
    > implementation from Xilinx (which I will eventually use for hardware
    > implementation), but I find it rather confusing (lack of vhdl
    > experience). Algorithm used, # of points, Radix#, bit precision do not
    > matter, as I'm looking for tutorial-like implementation.
    > The best example of what I'm looking for is (found using google)
    > http://www.opencores.org/projects.cgi/web/cf_fft/overview
    > http://www.opencores.org/cvsweb.shtml/fft/
    >
    > Thanks.
     
    =?iso-8859-1?B?VXRrdSDWemNhbg==?=, Nov 18, 2006
    #2
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  3. Student (confused)

    boysr2003

    Joined:
    Jul 27, 2006
    Messages:
    8
    FFT in VHDL

    Hi,
    my name is Yassir Boukhriss. You can use the core generator available in ISE foundation, and instantiate that in your top level code.
    Yassir Boukhriss
     
    boysr2003, Dec 2, 2006
    #3
  4. Student (confused)

    hussain.elsaid

    Joined:
    Dec 1, 2008
    Messages:
    3
    xilinx fft core

    Hello guys,

    I'm new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.

    here is what I do:

    1- from core generator I choose fft core and create .vhd & .vho & .xco files.
    2- I add the .xco & .vhd files to my project.
    3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.


    I'd appreciate if some one could help me with this, I'd be so grateful indeed.

    another question, in case I couldn't use the fft core I created an algorithm for a radix-2 and tried to write it in vhdl, but I'm not sure if I am going in the right way, following is the uncomplete code I'd appreciate if some one can tell me if it worth to complete the code like this or not;

    LIBRARY IEEE;
    USE IEEE.std_logic_1164.ALL;
    USE IEEE.numeric_std.ALL;

    PACKAGE untitled_pkg IS
    TYPE vector_of_std_logic_vector16 IS ARRAY (NATURAL RANGE <>) OF INTEGER;
    END untitled_pkg;

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    USE work.untitled_pkg.ALL;


    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity Hussain is

    generic(N:integer:=8;
    log:integer:=3);

    port(x:in vector_of_std_logic_vector16(0 TO 7);
    clk:in std_logic;
    y:eek:ut vector_of_std_logic_vector16(0 TO 7));
    end Hussain;

    architecture Behavioral of Hussain is

    begin

    top: process(clk)
    variable b,s,k,h,temp3,temp4:integer;
    variable temp:vector_of_std_logic_vector16(0 TO 7);
    variable temp1,temp2,w:integer;

    begin

    If rising_edge(clk)then

    temp:=x;


    loop1: for l in 1 to log loop
    b:=N/(2**l);
    s:=N/(2*b);

    loop2: for R in 1 to s loop
    h:=0; k:=0;
    loop3: for n in 0 to (b-1) loop


    wRom: case k is

    when 0 => w := 2;
    when 1 => w := 3;
    when 2 => w := 4;
    when 3 => w := 5;
    when others => null;
    end case;

    temp1:=temp(n+h)+temp(n+h+(b/2));
    temp2:=w*(temp(n+h)-temp(n+h+(b/2)));
    temp(n+h):=temp1;
    temp(n+h+(b/2)):=temp2;
    temp3:=k+s;
    k:=temp3;
    End loop;
    temp4:=h+(2*b);
    h:=temp4;
    End loop;
    End loop;
    End IF;
    Y<=temp;
    End process;

    end Behavioral;

    and thanks in advance;
    Hussain
     
    hussain.elsaid, Dec 4, 2008
    #4
  5. Student (confused)

    QuestaTechnologies

    Joined:
    Apr 19, 2010
    Messages:
    7
    Hi,
    Not sure if your testbench is correct.
    Try to simulate the design with another testbench.
    You can download and use the automatic testbench
    generators from http : // www . questatechnologies . com .
    Send mails to support @ questatechnologies . com .

    Hope this helps.

    Thanks.
     
    QuestaTechnologies, Apr 19, 2010
    #5
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