FIFO and SRAM

Discussion in 'VHDL' started by bat, Apr 1, 2008.

  1. bat

    bat

    Joined:
    Mar 28, 2008
    Messages:
    2
    Hi,

    As stated in a previous post ( Need a Simple SRAM Controller => still no reply), I'm new in VHDL and FPGA programming.

    I'm designing a camera processing fpga. My first task is to get data from a CMOS sensor and store it in a SRAM on an Opal Kelly XEM3050.

    I found many designs and source code for SDRAM controller, but none for SRAM. My first thought is that is because doing it for SRAM is simple, but maybe is it too obvious for me so that I don't get it... But this is not the point here.

    In all these designs, people used fifo's to "cache" data to and from the sdram. So my question is: should I do the same for a SRAM controller i.e. use a fifo to store data before reading or writing to the SRAM?

    Sorry if my question is stupid... Once again, I'm a real newbie...
     
    Last edited: Apr 1, 2008
    bat, Apr 1, 2008
    #1
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