FIFO depth and code

Discussion in 'VHDL' started by Marc, Jun 13, 2006.

  1. Marc

    Marc Guest

    Hi,
    I just started to work on a projekt where I need to interface to devices.
    One device has to send data (8 bit) to another.
    The sender has a lower clock speed than the receiver.
    I thought I might need a FIFO for doing this.
    Does anyone knows how I can calculate the depth (somany MB) for the ram?
    Examples of VHDL code for controlling the ram or complete design examples?

    Thanks,
    Marc
    --
    Marc, Jun 13, 2006
    #1
    1. Advertising

  2. Marc

    Alain Guest

    Marc a écrit :

    > Hi,
    > I just started to work on a projekt where I need to interface to devices.
    > One device has to send data (8 bit) to another.
    > The sender has a lower clock speed than the receiver.
    > I thought I might need a FIFO for doing this.
    > Does anyone knows how I can calculate the depth (somany MB) for the ram?
    > Examples of VHDL code for controlling the ram or complete design examples?
    >
    > Thanks,
    > Marc
    > --


    Hi Marc,

    Look at http://direct.xilinx.com/bvdocs/appnotes/xapp131.pdf
    There's also a reference design in vhdl (see the pdf file).
    Regards
    Alain, Jun 13, 2006
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.

Share This Page