FIFO depth and code

[Marc]

Hi,
I just started to work on a projekt where I need to interface to devices.
One device has to send data (8 bit) to another.
The sender has a lower clock speed than the receiver.
I thought I might need a FIFO for doing this.
Does anyone knows how I can calculate the depth (somany MB) for the ram?
Examples of VHDL code for controlling the ram or complete design examples?

Thanks,
Marc
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[Alain]

Marc a écrit :

Hi,
I just started to work on a projekt where I need to interface to devices.
One device has to send data (8 bit) to another.
The sender has a lower clock speed than the receiver.
I thought I might need a FIFO for doing this.
Does anyone knows how I can calculate the depth (somany MB) for the ram?
Examples of VHDL code for controlling the ram or complete design examples?

Thanks,
Marc
--

Hi Marc,

Look at http://direct.xilinx.com/bvdocs/appnotes/xapp131.pdf
There's also a reference design in vhdl (see the pdf file).
Regards