Fifo

Joined
Sep 2, 2008
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hi,i want to duplicate a bloc fifo so i use :
component fifo
port (

clock : in std_logic;
Reset : in std_logic;
WriteEnable : in std_logic;
ReadEnable : in std_logic;
DataIn : in std_logic_vector(31 downto 0);
DataOut : out std_logic_vector(31 downto 0);
FifoEmpty : out std_logic;
FifoFull : out std_logic
);
end component;
fifo_0 : fifo port map (
Reset => reset,
clock => clk,
DataIn => data_in_0,
WriteEnable => w0,
ReadEnable => rd0,
DataOut => wire5
);

fifo_1 : fifo port map (
Reset => reset,
clock => clk,
DataIn => data_in_1,
WriteEnable => w1,
ReadEnable => rd1,
DataOut => wire6
);
data_in 0 ,w0,wire5,.... are nodes to connect fifos to other blocs.
the problem that the duplication don't change the name of component,and it doesn't work in temporel(simulation with modelsim)
 
Joined
Sep 8, 2008
Messages
11
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0
Hi,

if I understand you right, you can solve this problem with a generate construct.
Your code would be like this:

PHP:
type t_slv_array is array(natural range <>) of std_logic_vector(31 downto 0);

signal data_in : t_slv_array(0 to 1);
signal wires : t_slv_array(0 to 1);
signal w  : std_logic_vector(0 to 1);
signal rd : std_logic_vector(0 to 1);
  
begin

  i_fifo_gen : for i in 0 to 1 generate
    i_fifo : fifo
      port map(
        Reset       => Reset,
        clock       => clk,
        DataIn      => data_in(i),
        WriteEnable => w(i),
        ReadEnable  => rd(i),
        DataOut     => wires(i),
        FifoEmpty   => open,
        FifoFull    => open
      );
  end generate i_fifo_gen;

Hope that helps you!

Bye, Steff
 

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