File Transfer

Discussion in 'VHDL' started by shashankrsharma, Mar 1, 2009.

  1. shashankrsharma

    shashankrsharma

    Joined:
    Mar 1, 2009
    Messages:
    6
    This Quote is regarding File Read operation into std_logic_vector.

    Is it possible to read a .txt or .doc file and convert the data inside it to binary (output: out std_logic_vector) and see in Test bench Waveform in VHDL???
    The output is of fixed length 150 downto 0, This is the packet data Which is further processed in MATLAB.. Plse help me in this issue...
    Last edited: Mar 1, 2009
    shashankrsharma, Mar 1, 2009
    #1
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  2. shashankrsharma

    ice

    Joined:
    Mar 3, 2009
    Messages:
    2

    Yes, check out the following libraries

    LIBRARY IEEE;
    USE ieee.std_logic_textio.all;
    LIBRARY std;
    USE std.textio.all;
    ice, Mar 3, 2009
    #2
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  3. shashankrsharma

    shashankrsharma

    Joined:
    Mar 1, 2009
    Messages:
    6
    Thanks folks,:veryprou:
    I have used the above lib, but the file reads the data into LINE data type,
    how to convert the data present in LINE to STD_LOGIC_VECTOR(150 down to 0)??

    I also faced another problem:oops: , later This code is to be simulated in MATLAB using Xilinx blockset, so i used BLACKBOX to call the program, but while execution there is a error reported -> "CODE ERROR" :!: stating IN and OUT keyword should not be used for FILE decleration..so how to correct that error??
    I know ppl rarely use such an concept, so if any one know plse do help:-( :stupido:
    shashankrsharma, Mar 4, 2009
    #3
  4. shashankrsharma

    shashankrsharma

    Joined:
    Mar 1, 2009
    Messages:
    6
    The source code

    this code is helpfull to copy contents from one file to another, but how to copy the contents in the std_logic_vector???
    check for the code->
    /////////////////////////////////////////////////////////////////////
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    library std;
    use std.textio.all;

    entity fileaccess is
    port(clk : in std_logic);
    end fileaccess;

    architecture Behavioral of fileaccess is
    file myfile:text is IN "in.txt";
    file outfile:text is out "out.txt";
    begin
    process(clk)
    variable eol:boolean;
    variable ilin,tempout:line;
    variable header,headerout:string(35 downto 1);
    variable tmp : integer;
    begin
    for tmp in 1 to 3 loop-- to copy 3 lines
    readline(myfile,ilin);
    read(ilin,header,eol);

    --headerout:=To_StdLogicVector(header);--????? how to do this:-( :stupido:
    --headerout<=to_std_logic_vector(header(1));--?????

    write(tempout,header);
    writeline(outfile,tempout);8)
    end loop;
    end process;
    end behavioral;
    ///////////////////////////////////////////////////////////////
    shashankrsharma, Mar 5, 2009
    #4
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