FIR ADDER IMPLEMENTATION

Discussion in 'VHDL' started by RealInfo, Feb 8, 2009.

  1. RealInfo

    RealInfo Guest

    Hi all

    What is the best FIR ADDER implemntation ?
    I mean the unit that adds all mulitlicanion results .

    The FIR output is > (Xn * Coefn) + (Xn-1 * Coefn-1) .....+ (Xn-k *
    Coefn-k )

    So the addition may be done in several ways : Arrray adder , accumulate
    adder , synthesiser originated adder of A + B + C +...N .

    The point is to make coding easier by avoiding RTL level coding and leting
    the synth to do the translation to gate level .

    My question is what is the best attitude , RTL coding or synt generated gate
    level ?

    Thanks in advance

    EC
    RealInfo, Feb 8, 2009
    #1
    1. Advertising

  2. RealInfo

    Barry Guest

    On Feb 8, 6:45 am, "RealInfo" <> wrote:
    > Hi all
    >
    > What is the best FIR ADDER implemntation ?
    > I mean the unit that adds all mulitlicanion results .
    >
    > The FIR  output is >  (Xn * Coefn)  +  (Xn-1 * Coefn-1)  .....+ (Xn-k *
    > Coefn-k )
    >
    > So the addition may be done in several ways : Arrray adder , accumulate
    > adder , synthesiser originated adder  of A + B + C +...N  .
    >
    > The point is to make coding easier by avoiding RTL level coding and leting
    > the synth to do the translation to gate level .
    >
    > My question is what is the best attitude , RTL coding or synt generated gate
    > level ?
    >
    > Thanks in advance
    >
    > EC


    It seems you are proposing to use the direct form FIR structure which
    has a very wide adder (A+B+C+...+N). Instead, you can use the
    equivalent transposed form FIR which only has two-input adders between
    registers, so it runs at a much higher clock rate. Any good DSP book
    will show you what the transposed form looks like - it's quite simple.

    Barry
    Barry, Feb 8, 2009
    #2
    1. Advertising

  3. RealInfo

    Guest

    On Feb 8, 11:50 am, Barry <> wrote:
    > On Feb 8, 6:45 am, "RealInfo" <> wrote:
    >
    >
    >
    > > Hi all

    >
    > > What is the best FIR ADDER implemntation ?
    > > I mean the unit that adds all mulitlicanion results .

    >
    > > The FIR  output is >  (Xn * Coefn)  +  (Xn-1 * Coefn-1)  ......+ (Xn-k *
    > > Coefn-k )

    >
    > > So the addition may be done in several ways : Arrray adder , accumulate
    > > adder , synthesiser originated adder  of A + B + C +...N  .

    >
    > > The point is to make coding easier by avoiding RTL level coding and leting
    > > the synth to do the translation to gate level .

    >
    > > My question is what is the best attitude , RTL coding or synt generated gate
    > > level ?

    >
    > > Thanks in advance

    >
    > > EC

    >
    > It seems you are proposing to use the direct form FIR structure which
    > has a very wide adder (A+B+C+...+N).  Instead, you can use the
    > equivalent transposed form FIR which only has two-input adders between
    > registers, so it runs at a much higher clock rate.  Any good DSP book
    > will show you what the transposed form looks like - it's quite simple.
    >
    > Barry


    What are the requirements for your design? While I fully support your
    goal of letting the synthesizer do most of the work for you, first you
    have to know exactly what it is that you want to build! In many
    cases, those annoying, pedestrian implementation considerations or
    overall performance problems will force you to get your hands dirty.
    For example, to make use of the SIMD mode of a Virtex DSP slice will
    probably require manual instantiation, or at least coding to a very
    device-specific style that is almost as baroque as the instantiation
    you wanted to avoid.

    If your data is much slower than the clock, you could use the MAC
    serial form for low resource usage. If your data is skinny you may be
    able to play tricks with SIMD modes. And so on. I've personally used
    lots of for-generate blocks to build a logarithmic adder tree in the
    past, but as has been pointed out, there are much better ways than
    that old brute-force-and-ignorance FIR.

    But ultimately, there is just no way that you will ever get from a
    simple VHDL two-line dot product expression to a well-implemented,
    optimal-for-your-application FIR filter just by counting on the
    synthesizer to do the right thing. At least not yet. You'll have to
    roll up your sleeves and get dirty coding :)

    - Kenn
    , Feb 9, 2009
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Sam Aborhey

    help please! 4bit adder/sub

    Sam Aborhey, Oct 17, 2004, in forum: VHDL
    Replies:
    3
    Views:
    4,201
    Jim Lewis
    Oct 19, 2004
  2. ALuPin

    30 bit adder performance

    ALuPin, Dec 10, 2004, in forum: VHDL
    Replies:
    5
    Views:
    614
    Pieter Hulshoff
    Dec 12, 2004
  3. Rune Christensen
    Replies:
    4
    Views:
    9,842
    David R Brooks
    Jan 22, 2005
  4. Emel
    Replies:
    1
    Views:
    5,364
    Mike Treseler
    Jan 16, 2006
  5. Rahul Iyer
    Replies:
    1
    Views:
    4,684
    gally
    Feb 20, 2008
Loading...

Share This Page