fixed pattern generator

Discussion in 'VHDL' started by alessandro basili, Sep 20, 2006.

  1. Hi to everyone, I need to design a fixed pattern generator on a serial
    link with more than 600 bits to be sent. Obviously the easiest way is to
    have a constant and shiftout the bits, but it will be a 600 and more
    flip-flops.
    I've never done this before, do you think there is a smarter way to do that?
    Thanks all

    Al

    p.s.: is to program from time to time an ASIC by the means of an fpga.
    alessandro basili, Sep 20, 2006
    #1
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  2. "alessandro basili" <> wrote in message
    news:eerirg$3jg$...
    > Hi to everyone, I need to design a fixed pattern generator on a serial
    > link with more than 600 bits to be sent. Obviously the easiest way is to
    > have a constant and shiftout the bits, but it will be a 600 and more
    > flip-flops.
    > I've never done this before, do you think there is a smarter way to do
    > that?
    > Thanks all
    >
    > Al
    >
    > p.s.: is to program from time to time an ASIC by the means of an fpga.


    The following component will give you a pseudorandom sequence, which I think
    should be more than 600 bits long

    entity SHIFT_REGISTER
    port ( RESET : in std_logic;
    CLOCK : in std_logic;
    DATA : out std_logic)
    end entity SHIFT_REGISTER;

    architecture RTL of SHIFT_REGISTER is
    signal STATE : std_logic_vector (7 downto 0);
    begin

    ITERATION: process (CLOCK)
    begin
    if CLOCK'event and CLOCK='1' then
    if RESET='1' then
    STATE <= "00000001";
    else
    STATE <= STATE(6 downto 0) & (STATE(7) xor STATE(2));
    end if;
    end if;
    end process ITERATION;

    DATA <= STATE(7);

    end architecture RTL;

    Pete
    Pete Bleackley, Sep 20, 2006
    #2
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  3. Sorry I didn't mention I need a fixed and known sequence of bits,
    actually I thought of an LSFR but my problem is how to implement it just
    that the sequence is the one I want?
    In principle yes, in practical I really don't have a clue!

    Pete Bleackley wrote:
    > "alessandro basili" <> wrote in message
    > news:eerirg$3jg$...
    >
    >>Hi to everyone, I need to design a fixed pattern generator on a serial
    >>link with more than 600 bits to be sent. Obviously the easiest way is to
    >>have a constant and shiftout the bits, but it will be a 600 and more
    >>flip-flops.
    >>I've never done this before, do you think there is a smarter way to do
    >>that?
    >>Thanks all
    >>
    >>Al
    >>
    >>p.s.: is to program from time to time an ASIC by the means of an fpga.

    >
    >
    > The following component will give you a pseudorandom sequence, which I think
    > should be more than 600 bits long
    >
    > entity SHIFT_REGISTER
    > port ( RESET : in std_logic;
    > CLOCK : in std_logic;
    > DATA : out std_logic)
    > end entity SHIFT_REGISTER;
    >
    > architecture RTL of SHIFT_REGISTER is
    > signal STATE : std_logic_vector (7 downto 0);
    > begin
    >
    > ITERATION: process (CLOCK)
    > begin
    > if CLOCK'event and CLOCK='1' then
    > if RESET='1' then
    > STATE <= "00000001";
    > else
    > STATE <= STATE(6 downto 0) & (STATE(7) xor STATE(2));
    > end if;
    > end if;
    > end process ITERATION;
    >
    > DATA <= STATE(7);
    >
    > end architecture RTL;
    >
    > Pete
    >
    >
    alessandro basili, Sep 20, 2006
    #3
  4. alessandro basili

    David Ashley Guest

    alessandro basili wrote:
    > Sorry I didn't mention I need a fixed and known sequence of bits,
    > actually I thought of an LSFR but my problem is how to implement it just
    > that the sequence is the one I want?
    > In principle yes, in practical I really don't have a clue!
    >
    > Pete Bleackley wrote:
    >
    >> "alessandro basili" <> wrote in message
    >> news:eerirg$3jg$...
    >>
    >>> Hi to everyone, I need to design a fixed pattern generator on a
    >>> serial link with more than 600 bits to be sent. Obviously the easiest
    >>> way is to have a constant and shiftout the bits, but it will be a 600
    >>> and more flip-flops.
    >>> I've never done this before, do you think there is a smarter way to
    >>> do that?


    Does the FPGA have BRAMs? Just declare an array of
    constants and have a clock going from address/enable
    to data out. The synthesizer should infer a BRAM.
    On xilinx BRAMS are 18K bits so you could get by with
    just one.

    -Dave

    --
    David Ashley http://www.xdr.com/dash
    Embedded linux, device drivers, system architecture
    David Ashley, Sep 20, 2006
    #4
  5. Unfortunately the chip doesn't have this feature, but even if I wouldn't
    use it because is a space application and you don't really want to have
    a flip in the configuration RAM of your device.
    I imagined that if there is a function which can calculate the exact
    sequence of an LSFR, I believe there can be a reverse function that,
    starting from the sequence, will give you the combinatorial input of the
    LFSR. Is this just impossible?
    I'm not talking about an implementable function, it can be even a C
    algorithm or whatever that gives you the correct combinatorial input
    from the sequence needed.

    David Ashley wrote:
    > alessandro basili wrote:
    >
    >>Sorry I didn't mention I need a fixed and known sequence of bits,
    >>actually I thought of an LSFR but my problem is how to implement it just
    >>that the sequence is the one I want?
    >>In principle yes, in practical I really don't have a clue!
    >>
    >>Pete Bleackley wrote:
    >>
    >>
    >>>"alessandro basili" <> wrote in message
    >>>news:eerirg$3jg$...
    >>>
    >>>
    >>>>Hi to everyone, I need to design a fixed pattern generator on a
    >>>>serial link with more than 600 bits to be sent. Obviously the easiest
    >>>>way is to have a constant and shiftout the bits, but it will be a 600
    >>>>and more flip-flops.
    >>>>I've never done this before, do you think there is a smarter way to
    >>>>do that?

    >
    >
    > Does the FPGA have BRAMs? Just declare an array of
    > constants and have a clock going from address/enable
    > to data out. The synthesizer should infer a BRAM.
    > On xilinx BRAMS are 18K bits so you could get by with
    > just one.
    >
    > -Dave
    >
    alessandro basili, Sep 21, 2006
    #5
  6. alessandro basili

    David Ashley Guest

    alessandro basili wrote:
    > Unfortunately the chip doesn't have this feature, but even if I wouldn't
    > use it because is a space application and you don't really want to have
    > a flip in the configuration RAM of your device.
    > I imagined that if there is a function which can calculate the exact
    > sequence of an LSFR, I believe there can be a reverse function that,
    > starting from the sequence, will give you the combinatorial input of the
    > LFSR. Is this just impossible?
    > I'm not talking about an implementable function, it can be even a C
    > algorithm or whatever that gives you the correct combinatorial input
    > from the sequence needed.
    >
    > David Ashley wrote:
    >
    >> alessandro basili wrote:
    >>
    >>> Sorry I didn't mention I need a fixed and known sequence of bits,
    >>> actually I thought of an LSFR but my problem is how to implement it just
    >>> that the sequence is the one I want?
    >>> In principle yes, in practical I really don't have a clue!
    >>>
    >>> Pete Bleackley wrote:
    >>>
    >>>
    >>>> "alessandro basili" <> wrote in message
    >>>> news:eerirg$3jg$...
    >>>>
    >>>>
    >>>>> Hi to everyone, I need to design a fixed pattern generator on a
    >>>>> serial link with more than 600 bits to be sent. Obviously the easiest
    >>>>> way is to have a constant and shiftout the bits, but it will be a 600
    >>>>> and more flip-flops.
    >>>>> I've never done this before, do you think there is a smarter way to
    >>>>> do that?

    >>
    >>
    >>
    >> Does the FPGA have BRAMs? Just declare an array of
    >> constants and have a clock going from address/enable
    >> to data out. The synthesizer should infer a BRAM.
    >> On xilinx BRAMS are 18K bits so you could get by with
    >> just one.
    >>
    >> -Dave
    >>


    Just declare a static array then, with no clocking.
    Given a 10 bit address, you get 1 bit out. Declare your
    600 bits of data as initialization to the array.
    0 => '0',
    1 => '1',
    2 => '1',
    3 => '0',
    ....

    The synthesizer will sort it all out. Don't have a clock and
    it won't use a bram. It will generate a function of the 10
    input bits that produces the output. It's not that hard to
    optimize such things, the synthesizer will handle it.

    -Dave


    --
    David Ashley http://www.xdr.com/dash
    Embedded linux, device drivers, system architecture
    David Ashley, Sep 21, 2006
    #6
  7. "alessandro basili" <> wrote in message
    news:eetcb7$rn4$...
    > Unfortunately the chip doesn't have this feature, but even if I wouldn't
    > use it because is a space application and you don't really want to have a
    > flip in the configuration RAM of your device.
    > I imagined that if there is a function which can calculate the exact
    > sequence of an LSFR, I believe there can be a reverse function that,
    > starting from the sequence, will give you the combinatorial input of the
    > LFSR. Is this just impossible?


    I've just found an online implementation of a function that will generate a
    LFSR for a given sequence

    http://ihome.ust.hk/~trippen/Cryptography/BM/frameset.html

    Pete
    Pete Bleackley, Sep 21, 2006
    #7
  8. This is really a very good idea! It will cost really small effort and
    even logic. Thanks a lot Dave

    David Ashley wrote:
    > alessandro basili wrote:
    >
    >>Unfortunately the chip doesn't have this feature, but even if I wouldn't
    >>use it because is a space application and you don't really want to have
    >>a flip in the configuration RAM of your device.
    >>I imagined that if there is a function which can calculate the exact
    >>sequence of an LSFR, I believe there can be a reverse function that,
    >>starting from the sequence, will give you the combinatorial input of the
    >>LFSR. Is this just impossible?
    >>I'm not talking about an implementable function, it can be even a C
    >>algorithm or whatever that gives you the correct combinatorial input
    >>from the sequence needed.
    >>
    >>David Ashley wrote:
    >>
    >>
    >>>alessandro basili wrote:
    >>>
    >>>
    >>>>Sorry I didn't mention I need a fixed and known sequence of bits,
    >>>>actually I thought of an LSFR but my problem is how to implement it just
    >>>>that the sequence is the one I want?
    >>>>In principle yes, in practical I really don't have a clue!
    >>>>
    >>>>Pete Bleackley wrote:
    >>>>
    >>>>
    >>>>
    >>>>>"alessandro basili" <> wrote in message
    >>>>>news:eerirg$3jg$...
    >>>>>
    >>>>>
    >>>>>
    >>>>>>Hi to everyone, I need to design a fixed pattern generator on a
    >>>>>>serial link with more than 600 bits to be sent. Obviously the easiest
    >>>>>>way is to have a constant and shiftout the bits, but it will be a 600
    >>>>>>and more flip-flops.
    >>>>>>I've never done this before, do you think there is a smarter way to
    >>>>>>do that?
    >>>
    >>>
    >>>
    >>>Does the FPGA have BRAMs? Just declare an array of
    >>>constants and have a clock going from address/enable
    >>>to data out. The synthesizer should infer a BRAM.
    >>>On xilinx BRAMS are 18K bits so you could get by with
    >>>just one.
    >>>
    >>>-Dave
    >>>

    >
    >
    > Just declare a static array then, with no clocking.
    > Given a 10 bit address, you get 1 bit out. Declare your
    > 600 bits of data as initialization to the array.
    > 0 => '0',
    > 1 => '1',
    > 2 => '1',
    > 3 => '0',
    > ...
    >
    > The synthesizer will sort it all out. Don't have a clock and
    > it won't use a bram. It will generate a function of the 10
    > input bits that produces the output. It's not that hard to
    > optimize such things, the synthesizer will handle it.
    >
    > -Dave
    >
    >
    alessandro basili, Sep 21, 2006
    #8
  9. I would try both solutions, even this is really incredibly nice!
    I'm enthusiast!!!

    Pete Bleackley wrote:
    > "alessandro basili" <> wrote in message
    > news:eetcb7$rn4$...
    >
    >>Unfortunately the chip doesn't have this feature, but even if I wouldn't
    >>use it because is a space application and you don't really want to have a
    >>flip in the configuration RAM of your device.
    >>I imagined that if there is a function which can calculate the exact
    >>sequence of an LSFR, I believe there can be a reverse function that,
    >>starting from the sequence, will give you the combinatorial input of the
    >>LFSR. Is this just impossible?

    >
    >
    > I've just found an online implementation of a function that will generate a
    > LFSR for a given sequence
    >
    > http://ihome.ust.hk/~trippen/Cryptography/BM/frameset.html
    >
    > Pete
    >
    >
    alessandro basili, Sep 21, 2006
    #9
  10. alessandro basili

    David Ashley Guest

    alessandro basili wrote:
    > This is really a very good idea! It will cost really small effort and
    > even logic. Thanks a lot Dave


    Do post the outcome of your experiments, closure is always nice.

    -Dave


    --
    David Ashley http://www.xdr.com/dash
    Embedded linux, device drivers, system architecture
    David Ashley, Sep 21, 2006
    #10
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