flip flop in mealy state machine

Discussion in 'VHDL' started by Ola, Nov 19, 2005.

  1. Ola

    Ola Guest

    Hi,
    I'm currently trying to make a control system for a project. I'm using
    the Mealy state machine consisting of two processes(state- and clk-
    process) to get the output signals. Unfortunately one of the signals has
    the same value as one of the input signals, but just one clock tact moved.
    First of all I used the commnad :
    signal1 <= signal2 after clock_tact
    and it works well. The problem is, that I'm not allowed to use this
    command, because the whole system is a synchronous model and not a
    testbench or library.
    I think, that the best way would be to use a flip flop, but I'm not
    quite sure if I can use it in a mealy machine (outside the processes).

    Can anyone answer this question?
    Maybe you have an idea how to make it in another way?

    Thank for help,
    Ola

    ---
    Findix Kleinanzeigen
    www.findix.com
    Ola, Nov 19, 2005
    #1
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  2. Ola wrote:

    > Maybe you have an idea how to make it in another way?


    I would use a synchronous process
    and declare variables for the state
    and output registers.

    -- Mike Treseler
    Mike Treseler, Nov 21, 2005
    #2
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