for generate

Discussion in 'VHDL' started by maniac89, Feb 25, 2009.

  1. maniac89

    maniac89

    Joined:
    Feb 22, 2009
    Messages:
    3
    can anyone tell me a simple example which use "FOR GENERATE" in vhdl?
    thanks!!!
    maniac89, Feb 25, 2009
    #1
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  2. maniac89

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    This is a (silly) example:
    Code:
    architecture structural of ADD4 is
      component FA is
        port(X, Y, Z : in std_logic;
             S, C : out std_logic);
      end component;
      signal C : std_logic_vector(4 downto 0);
    begin
    C(0) <= C0;
    gen: for i in 0 to 3 generate
      ADD: FA port map(A(i),B(i),C(i),S(i),C(i + 1));
    end generate gen;
    C4 <= C(4);
    end structural;
    It gives a synthesizable 4-bit adder, given the correct FA (full-adder) component;
    This isn't very serious code: You're likely to get better code using just the '+' operator.
    joris, Feb 25, 2009
    #2
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