For loop delay???

[krkrkr]

Hi all,

If I assign a signal before a long for loop in a process, will that signal wait until the end of the process to take place?

ie process (a) is
variable cnt : std_logic_vector(0 to 15) := X"0000";
begin
active <= '1';
for i 0 to 1000 loop
cnt := cnt + a;
end loop;
end process;

What if I want "active" take place once the process is activated and I don't want ot wait for the 1000 loop and reach the end of the process?

Regards.

 

[jeppe]

Will this be code for simulation or for synthesize (hardware implementation)
????

 

[krkrkr]

Its for hardware implimentation.

 

[jeppe]

OK - You must understand some basic principles behind VHDL.
You can't create delays in hardware with a loop statement.

In order to get fixed delays must you have a clock signal (with a fixed frequency)

 

[krkrkr]

Thanks Jeppe for your reply.

But I'm not looking to make a delay, I'm new to VHDL and I would like to understand the process concept.
I read that signal assignment in a process will take place at the end of the process, so what if I have a long for loop after the signal assignment? does that mean the signal assignment will not take place except when the for loop and all other statments finished?

If I want to design a logic that gives an active '1' once it comes in the process then do some other statments in the process, will this active signal comes to '1' just when it get in the process or at the end after all other statments in the process?

Regards.

 

[jeppe]

Hi Krkrkr
In that case will you get my "standard answer"
Search the net for the free interactive book on VHDL EVITA from actel
Specially chapter 6 will answer your questions about processes and signals

And yes your right - the loop will have to end before the assignment takes places - but in hardware will the loop not exist.

Jeppe