forcing external signals in VHDL 2008

Discussion in 'VHDL' started by MiguelM, Feb 5, 2011.

  1. MiguelM

    MiguelM

    Joined:
    Feb 5, 2011
    Messages:
    1
    Likes Received:
    0
    I’m trying to force an external signal in VHDL 2008

    First statement compiles without any errors
    my_local _sig <= <<signal .probe_all_dtypes_0.my_pure_vhd_sl : std_logic>>;

    Second statement produces an error during compilation:
    <<signal .probe_all_dtypes_0.my_pure_vhd_sl : std_logic>> <= force '1' ;

    What am I doing wrong? What would be a correct syntax for the second statement?
     
    MiguelM, Feb 5, 2011
    #1
    1. Advertisements

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Valentin Tihomirov

    Structural VHDL - Accesing signals of instances

    Valentin Tihomirov, Nov 1, 2003, in forum: VHDL
    Replies:
    2
    Views:
    732
    Paul Uiterlinden
    Nov 2, 2003
  2. Yttrium
    Replies:
    1
    Views:
    6,109
    David R Brooks
    Nov 27, 2003
  3. Naveen R

    VHDL global signals

    Naveen R, Dec 20, 2003, in forum: VHDL
    Replies:
    8
    Views:
    8,055
    Walter Dvorak
    Dec 26, 2003
  4. DonQ
    Replies:
    2
    Views:
    1,130
    Amontec Team, Laurent Gauch
    Feb 28, 2004
  5. Weddick

    Resynchronize external signals

    Weddick, Apr 1, 2005, in forum: VHDL
    Replies:
    6
    Views:
    935
    Mike Treseler
    Apr 2, 2005
  6. afd
    Replies:
    1
    Views:
    10,166
    Colin Paul Gloster
    Mar 23, 2007
  7. Eli Bendersky
    Replies:
    15
    Views:
    4,823
    Jonathan Bromley
    Apr 28, 2007
  8. hhanff
    Replies:
    8
    Views:
    1,226
    hhanff
    Jul 23, 2010
Loading...