forcing external signals in VHDL 2008

[MiguelM]

I’m trying to force an external signal in VHDL 2008

First statement compiles without any errors
my_local _sig <= <<signal .probe_all_dtypes_0.my_pure_vhd_sl : std_logic>>;

Second statement produces an error during compilation:
<<signal .probe_all_dtypes_0.my_pure_vhd_sl : std_logic>> <= force '1' ;

What am I doing wrong? What would be a correct syntax for the second statement?