formatted data

[leaf]

i have 7 controlled clocks as inout to my design.
(c0, c1, c2, c3, c4, c5, c6)

entity my_design is
port(
data_i : in std_logic;
c0, c1, c2, c3, c4, c5, c6 : in std_logic; -- clocks
format : in std_logic_vector(2 downto 0);
data_o : out std_logic
);

data_i is the reference data
c0, c1, c2, c3, c4, c5, c6 are the controlled clocks
format is the format selector
either:
NRZ - No Return to Zero
RTZ - Return to Zero
RTO - Return to One
SBC - Surrounded by complement
DCLKPOS - Double clock positive
DCLKNEG - Double clock negative

data_o is the formatted output data based on the controlled clocks and
the format and data

ex.
when data_i is 0 and c1 arrives, and when format = RTZ (return to
zero) data_o <= '1'
but when c2 arrives data_o <= '0' (or will return to zero)

based on that, how do i actually ouput to data_o the formatted data,

--yl

 

[leaf]

another example for this is:
when format is SBC (surrounded by complement)

c0'event and c0='1'
data_o <= not data_i
c1'event and c1='1'
data_o <= data_i
c2'event and c2 = '1'
data_o <= not data_i


something like that...

 

[backhus]

Hi leaf,
whatever you do with that many clocks it might work in simulation, but
synthesis will not allow more than one clock in a process.

Furthermore, you surely do not intend to build a gated clock like or-ing
all these clocks together or something?

If you want to build a data formatter that needs different speeds, why
don't you use your fastest clock and create a statemachine. The FSM can
create clock-enables for your datapath that work like you intend to do
with your C0 to C6 signals. Then the datapath code looks something like
this:



process(reset, masterclock)
begin
if reset = '1' then
-- whatever to reset
elsif masterclock'event and masterclock = '1' then
If C0_clockenable = '1' then
--do something
end if;

...

If C6_clockenable = '1' then
--do something
end if;
end if;
end process;

have a nice simulation

Eilert

 

[jens]

I'm confused here... the formats indicate asynchronous communications,
yet the incoming clocks indicate synchronous communications. Your best
bet might be to ignore the incoming clocks and recover your own clock.

 

[leaf]

backhus and jens,

I see, but what i'm doing is not for simulation, but for synthesis
I'll show you what i mean:

what is important here are the 6 clocks and the data_i and data_o
(1-bit)
we can just assume the format to be RTZ (Return to Zero)

w/c means,
when c0 clk arrives data_o gets the Value of data_i
when c1 clk arrives data_o goes HIGH
when c2 clk arrives data_o goes back to LOW

for this reason c3-c6 is not used.


another example: SBC (Surrounded by complement)
when c0 clk arrives data_o gets the Value of not(data_i)
when c1 clk arrives data_o gets the Value of data_i
when c2 clk arrives data_o gets the Value of not(data_i)
c3-c6 (not used).

 

[backhus]

backhus and jens,

I see, but what i'm doing is not for simulation, but for synthesis
I'll show you what i mean:

what is important here are the 6 clocks and the data_i and data_o
(1-bit)
we can just assume the format to be RTZ (Return to Zero)

w/c means,
when c0 clk arrives data_o gets the Value of data_i
when c1 clk arrives data_o goes HIGH
when c2 clk arrives data_o goes back to LOW

for this reason c3-c6 is not used.

Hi Leaf,
in my posting I wrote that synthesis does not allow more than one clock
in a process. So I had synthesis in my mind all the time.

I understand that you need, depending on the desired format, some but
not all clocks. But... where do these clocks come from? and how do they
look? From what you wrote above I expect something like this:
(please correct me if I'm wrong)


Just one bit of data for the first example:
_
c0 ____| |__________
_
c1 ______| |________
_
c2 ________| |______

Data_i ----<DDDDD>-----
_
Data_o ----<D| |_>-----

If that is right, and the clocks are not continuous (meaning 50% duty
cycle) then you can see them as clock enables for a masterclock as
described in my last posting.

Now, do you localy generate the c0..c6 signals (how?), or do they come
from an external source like data_i?

have a nice simulation (for as long as you are still designing )

Eilert

 

[leaf]

Clocks are from external source,
the data_i and data_o are 1-bit data

ex:
if data_i is 0

c0 ____| |__________
_
c1 ______| |________
_
c2 ________| |______ (not used)
__
data_i ___| |_______

format is Return to ONe

--yl

 

[backhus]

Clocks are from external source,
the data_i and data_o are 1-bit data

ex:
if data_i is 0

c0 ____| |__________
_
c1 ______| |________
_
c2 ________| |______ (not used)
__
data_i ___| |_______

format is Return to ONe

--yl

Hi Leaf,
must be some weird device that has data and multiple clocks (and the
format too?) on its outputs.

Are these signals synchronous to any clock of the system you are
designing? Probably not, or you wouldn't try to use the Cn-Signals as
Clocks for your design.

So to repeat your requirements as I understand them:
- data_i is a data bit that is stable for (how many) Clock impulses?
- c0..c6 are consecutive impulses, as shown above with c0..c2 followed
by c3..c6 (always?)?
- format tells you what kind of manipulation to data in shall be
performed to create data_o
- data_o is the formatted data output according to the format signal

The most proper design would be to use a clock that is at least twice as
fast as the Cn impulse length. Synchronize the Inputs with this clock
and design a nice FSM that formats your data. The width of the databits
will be multiples of the chosen clocks period, of course. But that may
be ok, if you chose the right frequency.

Another solution would be like this:

stage 1:
Use six flipflops, each clocked by one of your clock signals.
Store data_i in each ff.

stage 2:
calculate the values of the next six ffs (clocked by c0 only)
according to the format input.

stage 3:
create a and/or structure that enables each FFs output by one of the
clocks like this

data_o <= (c0 and q0) or (c1 and q1)....or (c6 and q6)

to serialize your data again.
The data_o is no longer a synchronous signal, so beware!

According to the format you might add some circuit that blanks out
unused clocks in the serialising stage if needed.

Again, this solution is not a very proper design and may have some
pitfalls in it, but basically it should work. the output data will be
delayed of course, but that shouldn't be a problem.

have a nice synthesis

Eilert

 

[leaf]

i have already finished the design for this,

data bit is stable for all the duration of all the clocks (c0..c6)
c0..c6 are consecutive, and it even have coinciding HIGH times
like this:
__
____| |_____
_____| |_______

so i have problems ORing the signals,

anyway

my design fell into somewhat a State machine,
The UPPER part controls the FORMAT and orchestrates the clocks (c0..c6)
But still i did use OR, XOR and AND for some clocks

the LOWER part is a DFF (with PRESET, RESET and CLOCK connected to VCC)