fpga clock resolution

[niyander]

hello,

can some one tell me what is the clock resolution in FPGA, basically i
want to know if xilinx spartan-3 works in nano seconds or in micro
seconds.
i have a written an vhdl coding and i get the following result in the
ISE, so if i provide external clock of 100 Mhz then will i get the
output in about 7 nano seconds?
sorry for my silly question since i am new in VHDL.

Speed Grade: -5

Minimum period: 10.663ns (Maximum Frequency: 93.785MHz)
Minimum input arrival time before clock: 3.325ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found

thanks

 

[KJ]

hello,

can some one tell me what is the clock resolution in FPGA, basically i
want to know if xilinx spartan-3 works in nano seconds or in micro
seconds.
Nano

i have a written an vhdl coding and i get the following result in the
ISE, so if i provide external clock of 100 Mhz then will i get the
output in about 7 nano seconds?

Neither statement is correct. The minimum period listed below is
10.663 ns (or 93.785 MHz). If you were to clock the design at 100 MHz
then it would not be guaranteed to operate under all temperature and
voltage conditions. In general, even if you know exactly what *your*
operating temp/voltage conditions are, it is still difficult to
estimate whether or not you can overclock your design to run at 100
MHz.

The clock to output delay that you listed is 6.216 ns which means that
under all operating conditions that are within specification, the
output signal will come out no more than 6.216ns after the rising edge
of the clock (not 7ns as you stated).

sorry for my silly question since i am new in VHDL.

That's one way you learn though...asking questions. I should point
out though that neither of the questions you asked had anything to do
with VHDL.

KJ

 

[niyander]

Neither statement is correct.  The minimum period listed below is
10.663 ns (or 93.785 MHz).  If you were to clock the design at 100 MHz
then it would not be guaranteed to operate under all temperature and
voltage conditions.  In general, even if you know exactly what *your*
operating temp/voltage conditions are, it is still difficult to
estimate whether or not you can overclock your design to run at 100
MHz.

The clock to output delay that you listed is 6.216 ns which means that
under all operating conditions that are within specification, the
output signal will come out no more than 6.216ns after the rising edge
of the clock (not 7ns as you stated).


That's one way you learn though...asking questions.  I should point
out though that neither of the questions you asked had anything to do
with VHDL.

KJ

thank you KJ... ^_^
one more question please,
what's the use of IOB in FPGA? I have written a floating point
multiplier and in synthesis summery I can see 99 IOB used.
How can i reduce IOB usage?

thanks