fpga clock resolution

Discussion in 'VHDL' started by niyander, Oct 27, 2009.

  1. niyander

    niyander Guest

    hello,

    can some one tell me what is the clock resolution in FPGA, basically i
    want to know if xilinx spartan-3 works in nano seconds or in micro
    seconds.
    i have a written an vhdl coding and i get the following result in the
    ISE, so if i provide external clock of 100 Mhz then will i get the
    output in about 7 nano seconds?
    sorry for my silly question since i am new in VHDL.

    Speed Grade: -5

    Minimum period: 10.663ns (Maximum Frequency: 93.785MHz)
    Minimum input arrival time before clock: 3.325ns
    Maximum output required time after clock: 6.216ns
    Maximum combinational path delay: No path found

    thanks
     
    niyander, Oct 27, 2009
    #1
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  2. niyander

    KJ Guest

    On Oct 27, 4:33 pm, niyander <> wrote:
    > hello,
    >
    > can some one tell me what is the clock resolution in FPGA, basically i
    > want to know if xilinx spartan-3 works in nano seconds or in micro
    > seconds.


    Nano

    > i have a written an vhdl coding and i get the following result in the
    > ISE, so if i provide external clock of 100 Mhz then will i get the
    > output in about 7 nano seconds?


    Neither statement is correct. The minimum period listed below is
    10.663 ns (or 93.785 MHz). If you were to clock the design at 100 MHz
    then it would not be guaranteed to operate under all temperature and
    voltage conditions. In general, even if you know exactly what *your*
    operating temp/voltage conditions are, it is still difficult to
    estimate whether or not you can overclock your design to run at 100
    MHz.

    The clock to output delay that you listed is 6.216 ns which means that
    under all operating conditions that are within specification, the
    output signal will come out no more than 6.216ns after the rising edge
    of the clock (not 7ns as you stated).

    > sorry for my silly question since i am new in VHDL.
    >


    That's one way you learn though...asking questions. I should point
    out though that neither of the questions you asked had anything to do
    with VHDL.

    KJ
     
    KJ, Oct 28, 2009
    #2
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  3. niyander

    niyander Guest

    On Oct 28, 5:25 am, KJ <> wrote:
    > On Oct 27, 4:33 pm, niyander <> wrote:
    >
    > > hello,

    >
    > > can some one tell me what is the clock resolution in FPGA, basically i
    > > want to know if xilinx spartan-3 works in nano seconds or in micro
    > > seconds.

    >
    > Nano
    >
    > > i have a written an vhdl coding and i get the following result in the
    > > ISE, so if i provide external clock of 100 Mhz then will i get the
    > > output in about 7 nano seconds?

    >
    > Neither statement is correct.  The minimum period listed below is
    > 10.663 ns (or 93.785 MHz).  If you were to clock the design at 100 MHz
    > then it would not be guaranteed to operate under all temperature and
    > voltage conditions.  In general, even if you know exactly what *your*
    > operating temp/voltage conditions are, it is still difficult to
    > estimate whether or not you can overclock your design to run at 100
    > MHz.
    >
    > The clock to output delay that you listed is 6.216 ns which means that
    > under all operating conditions that are within specification, the
    > output signal will come out no more than 6.216ns after the rising edge
    > of the clock (not 7ns as you stated).
    >
    > > sorry for my silly question since i am new in VHDL.

    >
    > That's one way you learn though...asking questions.  I should point
    > out though that neither of the questions you asked had anything to do
    > with VHDL.
    >
    > KJ


    thank you KJ... ^_^
    one more question please,
    what's the use of IOB in FPGA? I have written a floating point
    multiplier and in synthesis summery I can see 99 IOB used.
    How can i reduce IOB usage?

    thanks
     
    niyander, Oct 28, 2009
    #3
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