Frequency Doubler in VHDL with symmetric duty cycle

[Gazelle]

Good day gents,
I am wondering if VHDL (or Verilog) code exists in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric duty cycle.
Below some code can be found which generates a by-2 multiplied frequency - however the duty cycle
is very assymmetrical ...

Many thanks for your input !

Regards,

Michel


-- Frequency Doubler using DFF
-- code in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo = 2*fi
end F2;


architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;


begin
process (clk) begin
if (clk 'event and clk = '1') then
q <= notq;
end if;
end process;

notq <= not q ;
clk <= (notq xnor fi) ;
fo <= clk;

end behav;