From which memory-deep it is more meaningfully to use a RAM

Discussion in 'VHDL' started by calzinide@yahoo.de, Mar 8, 2006.

  1. Guest

    I am searching for the border when it is meaningfull to use a RAM or
    RegisterFile instead of of a RTL register description. Has someone
    empirical values when it is better to use RAM hardmacros to save area ?

    Thanks calzi
     
    , Mar 8, 2006
    #1
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  2. On 7 Mar 2006 23:49:38 -0800, wrote:

    >I am searching for the border when it is meaningfull to use a RAM or
    >RegisterFile instead of of a RTL register description. Has someone
    >empirical values when it is better to use RAM hardmacros to save area ?


    You don't mention the target architecure.

    For Xilinx FPGAs, there is a small 16 location RAM that only uses one
    LUT for single port or two LUTs for dual port (r + r/w).
    This means it is more efficient in terms of space to use a RAM instead
    of flip flops for even the tiniest memories.

    For an ASIC, the threshold would be much larger.

    Regards,
    Allan
     
    Allan Herriman, Mar 8, 2006
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  3. Andy Guest

    My experience with FPGAs has indicated that anything above 3x has a
    definite benefit in clb ram. Note however, than the latest Virtex4
    have only half of their clb luts can be rams, but I doubt that would
    make a difference for when it is best to use rams or not. OTOH, if it
    takes significant overhead to manage the fact that you only have read
    access to one or two "registers" at a time in a ram, then the threshold
    may get much higher.

    I would also strongly suggest you use your synthesis tool's ability to
    infer ram from arrays, rather than instantiating macros for ram, unless
    you are using some of the advanced features of block rams that cannot
    be inferred from RTL. Inferred rams can store non-std_logic type data,
    such as integers, booleans, enums, etc., and are indexed with integers,
    both of which make for much faster simulations.

    Andy Jones
     
    Andy, Mar 8, 2006
    #3
  4. wrote:
    > I am searching for the border when it is meaningfull to use a RAM or
    > RegisterFile instead of of a RTL register description. Has someone
    > empirical values when it is better to use RAM hardmacros to save area ?



    I have had no reason to use a vendor macro.
    I use a standard blockram template that works
    for both brandX and A. For some minimum dimensions, synthesis
    makes a block ram, for others I get registers.

    -- Mike Treseler
     
    Mike Treseler, Mar 8, 2006
    #4
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