FSM IOB problem

[Eric]

Hi guys, im trying to synthasize an FSM into a Xilinx Spartan-3 and
keep getting problems with IOB usage....here is part of the report:

Design Statistics
# IOs : 263

Cell Usage :
# BELS : 135
# LUT2 : 132
# LUT3 : 3
# FlipFlops/Latches : 134
# FDC : 3
# FDP : 1
# LD_1 : 130
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 261
# IBUF : 131
# OBUF : 130
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200tq144-4

Number of Slices: 78 out of 1920 4%
Number of Slice Flip Flops: 134 out of 3840 3%
Number of 4 input LUTs: 135 out of 3840 3%
Number of bonded IOBs: 261 out of 97 269% (*)
Number of GCLKs: 1 out of 8 12%

WARNING:Xst:1336 - (*) More than 100% of Device resources are used

Im a begginer to synthesis so im not sure if this is a problem with my
coding style or synthesis settings. Would appreaciate any tips. Thanks

Eric

 

[Mohammed A khader]

Hi Eric,

Whats your top entity interface.

Mohammed A Khader.

 

[Eric]

Hi Eric,

Whats your top entity interface.

Mohammed A Khader.

ive fixed the problem, turned IOBs off in the synth tool. I do have
some latches which i dont know how to remove. I save values into a
record type variable, and i need several cycles (reading off a ram) to
fill all the values, i then output the record variable. How do i do
this without infering latches.......i understand that its innevitable
since im saving values. tips?

Eric

 

[aa55]

Latches are usually inferred in a combinatorial process that doesn't
assign a value to a signal for every condition.
e.g.
process
begin
case sel is
when "00" => a<=b;
when "01" => a<=c;
when others => null;
end process;
Since "a" isn't assign a value for when others it has to store it's
value by using a latch. To avoid this ensure that you assign a value to
"a" for all conditions.

Send a sample of your code and maybe we can help...