C
Charlie
Hello,
I'm trying to code a simple state machine in VHDL. When I simulate it it
seems to run okay, but when I run it for real inside an FPGA it just seems
to get stuck in the first state. The first state has an IF statement in it,
if I remove this IF statement the FSM runs without getting stuck. The
following shows how I have coded the FSM:
state_machine : process(RST, FAST_CLK)
begin
if RST = '0' then
fsm_state <= IDLE;
elsif FAST_CLK'event and FAST_CLK = '1' then
case fsm_state is
when IDLE =>
fsm_state <= STATE_00;
when STATE_00 =>
if SIG_A = SIG_B then -- just 2 signals
fsm_state <= STATE_01;
else
fsm_state <= STATE_02;
end if;
when STATE_01 =>
I'm trying to code a simple state machine in VHDL. When I simulate it it
seems to run okay, but when I run it for real inside an FPGA it just seems
to get stuck in the first state. The first state has an IF statement in it,
if I remove this IF statement the FSM runs without getting stuck. The
following shows how I have coded the FSM:
state_machine : process(RST, FAST_CLK)
begin
if RST = '0' then
fsm_state <= IDLE;
elsif FAST_CLK'event and FAST_CLK = '1' then
case fsm_state is
when IDLE =>
fsm_state <= STATE_00;
when STATE_00 =>
if SIG_A = SIG_B then -- just 2 signals
fsm_state <= STATE_01;
else
fsm_state <= STATE_02;
end if;
when STATE_01 =>