fsm state encodings

Discussion in 'VHDL' started by Caterpillar, Feb 10, 2006.

  1. Caterpillar

    Caterpillar Guest

    Dear all,
    I want to optimize the state encoding of a FSM. I've typed this
    declarations

    type STATETYPE is std_logic_vector(1 downto 0); -- state declaration
    constant IDLE : STATETYPE := "00";
    constant EN_MUX1_DEMUX : STATETYPE := "01";
    constant EN_MUX2 : STATETYPE := "11";
    constant RST_FF : STATETYPE := "10";
    signal CURRENT_STATE : STATETYPE;
    signal NEXT_STATE : STATETYPE; -- signals
    declaration

    then I've used the usually 3-process coding style, with case
    statements.
    Modelsim gives me this error

    near "std_logic_vector": expecting: '(' ACCESS ARRAY FILE RANGE RECORD
    PROTECTED

    What's wrong?

    Thank you

    Cat
     
    Caterpillar, Feb 10, 2006
    #1
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  2. Caterpillar

    Guest

    Cat,
    try subtype STATETYPE ...

    std_logic_vector is a type so STATETYPE is a subtype.

    Charles
     
    , Feb 10, 2006
    #2
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