FSM typical

Discussion in 'VHDL' started by engrjet, Mar 31, 2008.

  1. engrjet

    engrjet

    Joined:
    Jan 29, 2008
    Messages:
    4
    Hi
    I'm facing a problem in FSM design.
    If I use only a single state signal and modify it on clk it works
    But if I use the conventional way of present_state<= next_state on clk and change the next_state on present state it does not work.
    What can be the problem And its solution.
    Please help.

    Thanks and Regards
    engrjet
     
    engrjet, Mar 31, 2008
    #1
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  2. engrjet

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
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    Location:
    Denmark
    jeppe, Mar 31, 2008
    #2
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  3. engrjet

    engrjet

    Joined:
    Jan 29, 2008
    Messages:
    4
    No !
    I think I failed to explain the problem to you.
    process(clk, rst)
    begin
    if rst = '0'
    present_state<= reset;
    elsif clk'event and clk= '1' then
    present_state<= next_state;
    end if;
    end process;
    process(present_state,.....)-- all the asynchronous signals for change of state.
    case present_state is
     
    engrjet, Apr 1, 2008
    #3
  4. engrjet

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Code:
    
    
    process(clk, rst)
    begin
    if rst = '0'
    present_state<= reset;
    elsif clk'event and clk= '1' then
    present_state<= next_state;
    end if;
    end process;

    process(present_state,.....)-- all the asynchronous signals for change of state.
    Next_state <= Present_state; -- TRY THIS LINE
    case present_state is
     
    jeppe, Apr 1, 2008
    #4
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