FSM with more than 1 input at each state

[swiss student]

hello every one

There are 10 states in my design,the next state depends on more than
one inputs.Now when i compile my code it gives me error as no feasible
entries

the code is as follows
ENTITY YYYY IS
port(
clk : IN std_logic;
rst : IN std_logic;
M1_IN,M2_IN,M3_IN,M4_IN,M5_IN : IN std_logic;
M6_IN : IN work.mux_range.sel_range
M1_OUT,M2_OUT,M3_OUT,M4_OUT,M5_OUT: OUT std_logic;
M6_OUT :OUT work.mux_range.sel_range);

END ENTITY;

The part of the of code for calculating the next state is as follows

when s4=>
IF (M5_IN='0' and M6_IN = '4') THEN
next_state<= s5;
else
next_state<=s4;
END IF;

can some one tell if there is some prob in this code

please let me know wat changes i need to make

suresh

 

[Eyck Jentzsch]

hello every one

There are 10 states in my design,the next state depends on more than
one inputs.Now when i compile my code it gives me error as no feasible
entries

the code is as follows
ENTITY YYYY IS
port(
clk : IN std_logic;
rst : IN std_logic;
M1_IN,M2_IN,M3_IN,M4_IN,M5_IN : IN std_logic;
M6_IN : IN work.mux_range.sel_range
M1_OUT,M2_OUT,M3_OUT,M4_OUT,M5_OUT: OUT std_logic;
M6_OUT :OUT work.mux_range.sel_range);

END ENTITY;

The part of the of code for calculating the next state is as follows

when s4=>
IF (M5_IN='0' and M6_IN = '4') THEN

^^^^^^^^^^^^
M6_IN is of type work.mux_range.sel_range so the compiler does not know,
how to interpret the '4' (neither the newsgroup does since you did not
provide the definition).

next_state<= s5;
else
next_state<=s4;
END IF;

can some one tell if there is some prob in this code

please let me know wat changes i need to make

suresh

-Eyck

 

[aaaaaa]

Hi Suresh,
U are checking the value of M6_in as 4 but u have declared as some other
type. Kindly match the both , I hope that problem will be resolved.
Rgds
Anupam Garg