function and its hardware?

Discussion in 'VHDL' started by Pasacco, Dec 18, 2006.

  1. Pasacco

    Pasacco Guest

    Hi

    I am having problem synthesizing VHDL functions and mapping in Xilinx
    FPGA.
    Simulation is working as expected.
    But it is not working after synthesis (and implementation).
    It seems that 'latches' are used and they are NOT functioning.
    (I heard that we better use "flip flop" rather than 'latch' in FPGA)
    Problem is following.

    I wrote two simple functions.
    One function generates 'multiplexor'.
    The other function generates "multiplexor select signal".
    Each function looks like below.
    I need these "variable initializations".
    In case latches generated for "MUX_OUT" and "MUX_SEL_OUT" signals are
    problems,
    can anyone help me with working around this problem? Thankyou.
    ------------------------------------------------------------------------------------
    --- function 1 : very simple multiplexor
    ------------------------------------------------------------------------------------
    function MUX_FUNC( Temp: <some type> ) return integer is
    variable MUX_OUT : integer;
    begin
    MUX_OUT := 0; /* this part is unclear */
    if <some condition> then MUX_OUT := 0;
    else
    for <loop range> loop
    if <some condition> then
    MUX_OUT := <some value>;
    end if;
    end loop;
    end if;
    return MUX_OUT;
    end MUX_FUNC;
    -----------------------------------------------------------------------------------
    -- function 2 : very simple "mux select signal generator"
    ------------------------------------------------------------------------------------
    function MUX_SEL_FUNC( Temp: <some type> ) return <some type> is

    variable MUX_SEL_OUT : <some type>;
    begin
    MUX_SEL_OUT := 0; /* this part is unclear */
    Loop1: for <loop range> loop
    if <some condition> then
    MUX_SEL_OUT := <some value>
    end if;
    end loop;
    return MUX_SEL_OUT;
    end MUX_SEL_FUNC;
    Pasacco, Dec 18, 2006
    #1
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  2. Pasacco wrote:


    > It seems that 'latches' are used and they are NOT functioning.


    If so in many cases you have been trapped into the "muxed latch
    problem": A mux chooses the value that has to be loaded into the latch.
    If the mux-selector and the latch-enable are not independent then the
    mux may output a new value before the latch is closed.


    > function MUX_FUNC( Temp: <some type> ) return integer is
    > variable MUX_OUT : integer;
    > begin
    > MUX_OUT := 0; /* this part is unclear */
    > if <some condition> then MUX_OUT := 0;
    > else
    > for <loop range> loop
    > if <some condition> then
    > MUX_OUT := <some value>;
    > end if;
    > end loop;
    > end if;
    > return MUX_OUT;
    > end MUX_FUNC;


    As far as I see it there will be no latch inferred because of this
    function. Always a value will be assigned to the output variable ->
    combinational logic.

    It depends on what you do with the result of the function: combinational
    logic, latch or flipflop.

    Ralf
    Ralf Hildebrandt, Dec 27, 2006
    #2
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  3. Pasacco

    Rob Dekker Guest

    Hi Pasacco,

    This does not sound right. There should be no latches here.

    The local variables MUX_OUT or MUX_SEL_OUT have limited lifetime, and are automatically initialized to integer'left.
    So, even without the initial assignment they should NEVER create a latch.

    This is either a bug in the synthesis tool (which one are you using?) or the latches come from some signal or variable OUTSIDE the
    function.
    Only way to know is if you show a bit more of the design.

    So : Can you give the 'process' statement(s) (or other context) in which these functions are called ?

    Rob


    "Pasacco" <> wrote in message news:...
    > Hi
    >
    > I am having problem synthesizing VHDL functions and mapping in Xilinx
    > FPGA.
    > Simulation is working as expected.
    > But it is not working after synthesis (and implementation).
    > It seems that 'latches' are used and they are NOT functioning.
    > (I heard that we better use "flip flop" rather than 'latch' in FPGA)
    > Problem is following.
    >
    > I wrote two simple functions.
    > One function generates 'multiplexor'.
    > The other function generates "multiplexor select signal".
    > Each function looks like below.
    > I need these "variable initializations".
    > In case latches generated for "MUX_OUT" and "MUX_SEL_OUT" signals are
    > problems,
    > can anyone help me with working around this problem? Thankyou.
    > ------------------------------------------------------------------------------------
    > --- function 1 : very simple multiplexor
    > ------------------------------------------------------------------------------------
    > function MUX_FUNC( Temp: <some type> ) return integer is
    > variable MUX_OUT : integer;
    > begin
    > MUX_OUT := 0; /* this part is unclear */
    > if <some condition> then MUX_OUT := 0;
    > else
    > for <loop range> loop
    > if <some condition> then
    > MUX_OUT := <some value>;
    > end if;
    > end loop;
    > end if;
    > return MUX_OUT;
    > end MUX_FUNC;
    > -----------------------------------------------------------------------------------
    > -- function 2 : very simple "mux select signal generator"
    > ------------------------------------------------------------------------------------
    > function MUX_SEL_FUNC( Temp: <some type> ) return <some type> is
    >
    > variable MUX_SEL_OUT : <some type>;
    > begin
    > MUX_SEL_OUT := 0; /* this part is unclear */
    > Loop1: for <loop range> loop
    > if <some condition> then
    > MUX_SEL_OUT := <some value>
    > end if;
    > end loop;
    > return MUX_SEL_OUT;
    > end MUX_SEL_FUNC;
    >
    Rob Dekker, Dec 29, 2006
    #3
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