Function Call

Discussion in 'VHDL' started by Matt North, Oct 23, 2003.

  1. Matt North

    Matt North Guest

    Ive got a package called ITRON_VFD which holds a function called CPosition,
    Both the package and code calling the function are shown below,
    compiling in Leonardo gives the following error -- pkg_test.vhd",line 17:
    Error, no feasible entries for subprogram CPosition.
    compiling in Modelsim gives the following error --pkg_test.vhd(18): type
    error resolving function call: cposition

    --Package
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    package ITRON_VFD is

    type matrix is array (0 to 2) of bit_vector(7 downto 0);

    function CPosition (x, y: bit_vector(7 downto 0)) return matrix;

    end ITRON_VFD;

    package body ITRON_VFD is

    function CPosition (x, y: bit_vector(7 downto 0))
    return matrix is variable result: matrix;

    constant sc: bit_vector(7 downto 0) := X"10";
    type matrix is array (NATURAL range <>) of bit_vector(7 downto 0);

    begin

    result:=(sc, x, y);

    return result;
    end CPosition;

    end ITRON_VFD;

    --Code
    library IEEE;
    use IEEE.std_logic_1164.all;
    use WORK.ITRON_VFD.all;

    entity test is
    port(clk, rst : in std_logic;
    outp : out bit_vector(7 downto 0));
    end test;

    architecture rtl of test is
    type abc is array (0 to 2) of bit_vector(7 downto 0);
    signal ram: abc;
    subtype int_r is integer range 0 to abc'HIGH+1;
    signal n: int_r;
    begin

    ram<=CPosition(X"23", X"44");

    process(clk, rst, n, ram)
    begin
    if rising_edge(clk) then
    if rst='0' or n=abc'HIGH+1 then
    outp<=X"00";
    n<=0;
    elsif n<abc'HIGH+1 then
    outp<=ram(n);
    n<=n+1;
    end if;
    end if;
    end process;

    end rtl;

    This is my first project using function calls from my own package and as far
    as i can see there isnt any type conflict between the two, the function
    expects two bit vectors of length 8 and returns an array of bit vectors.
    Any clues.

    Thanks,
    Matt
     
    Matt North, Oct 23, 2003
    #1
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  2. Matt North

    Jim Lewis Guest

    Matt,
    The messages are telling you that there is no
    function called CPosition that returns a value
    that is of type abc. Note that types abc and matrix
    are distinct types. You declared matrix in the
    package. This type is visible in the entity, so
    use it. Same notes are below.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


    Matt North wrote:
    > Ive got a package called ITRON_VFD which holds a function called CPosition,
    > Both the package and code calling the function are shown below,
    > compiling in Leonardo gives the following error -- pkg_test.vhd",line 17:
    > Error, no feasible entries for subprogram CPosition.
    > compiling in Modelsim gives the following error --pkg_test.vhd(18): type
    > error resolving function call: cposition
    >
    > --Package
    > library ieee;
    > use ieee.std_logic_1164.all;
    > use ieee.numeric_std.all;
    >
    > package ITRON_VFD is
    >
    > type matrix is array (0 to 2) of bit_vector(7 downto 0);

    You would have greater flexability here if the dimension (0 to 2)
    were unconstrained (like you did below)

    >
    > function CPosition (x, y: bit_vector(7 downto 0)) return matrix;
    >
    > end ITRON_VFD;
    >
    > package body ITRON_VFD is
    >
    > function CPosition (x, y: bit_vector(7 downto 0))
    > return matrix is variable result: matrix;
    >
    > constant sc: bit_vector(7 downto 0) := X"10";
    > type matrix is array (NATURAL range <>) of bit_vector(7 downto 0);

    This does not need to be here. Remove it. See note
    above, you may want this as your declaration above.

    >
    > begin
    >
    > result:=(sc, x, y);
    >
    > return result;
    > end CPosition;
    >
    > end ITRON_VFD;
    >
    > --Code
    > library IEEE;
    > use IEEE.std_logic_1164.all;
    > use WORK.ITRON_VFD.all;
    >
    > entity test is
    > port(clk, rst : in std_logic;
    > outp : out bit_vector(7 downto 0));
    > end test;
    >
    > architecture rtl of test is
    > type abc is array (0 to 2) of bit_vector(7 downto 0);


    Type abc is not the same as matrix.
    You can remove this declaration.

    > signal ram: abc;

    You must use type matrix here.

    > subtype int_r is integer range 0 to abc'HIGH+1;

    If you delete abc above, you might wish to use matrix here.

    > signal n: int_r;
    > begin
    >
    > ram<=CPosition(X"23", X"44");
    >
    > process(clk, rst, n, ram)
    > begin
    > if rising_edge(clk) then
    > if rst='0' or n=abc'HIGH+1 then
    > outp<=X"00";
    > n<=0;
    > elsif n<abc'HIGH+1 then
    > outp<=ram(n);
    > n<=n+1;
    > end if;
    > end if;
    > end process;
    >
    > end rtl;
    >
    > This is my first project using function calls from my own package and as far
    > as i can see there isnt any type conflict between the two, the function
    > expects two bit vectors of length 8 and returns an array of bit vectors.
    > Any clues.
    >
    > Thanks,
    > Matt
    >
    >
     
    Jim Lewis, Oct 23, 2003
    #2
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  3. Matt North

    Matt North Guest

    Jim,

    I thought that because both abc, and matrix had the same physical size
    (array of 3 bytes of type bit_vector)
    that it wouldnt differentiate between the two
    This may cause problems as i hope to have many functions in a package which
    all o/p arrays of varying lengths (all of type bit_vector)
    which will be i/p into one big array in the entity!

    Thanks for your help,
    Matt

    "Jim Lewis" <> wrote in message
    news:...
    > Matt,
    > The messages are telling you that there is no
    > function called CPosition that returns a value
    > that is of type abc. Note that types abc and matrix
    > are distinct types. You declared matrix in the
    > package. This type is visible in the entity, so
    > use it. Same notes are below.
    >
    > Cheers,
    > Jim
    > --
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Jim Lewis
    > Director of Training mailto:
    > SynthWorks Design Inc. http://www.SynthWorks.com
    > 1-503-590-4787
    >
    > Expert VHDL Training for Hardware Design and Verification
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    >
    >
    > Matt North wrote:
    > > Ive got a package called ITRON_VFD which holds a function called

    CPosition,
    > > Both the package and code calling the function are shown below,
    > > compiling in Leonardo gives the following error -- pkg_test.vhd",line

    17:
    > > Error, no feasible entries for subprogram CPosition.
    > > compiling in Modelsim gives the following error --pkg_test.vhd(18): type
    > > error resolving function call: cposition
    > >
    > > --Package
    > > library ieee;
    > > use ieee.std_logic_1164.all;
    > > use ieee.numeric_std.all;
    > >
    > > package ITRON_VFD is
    > >
    > > type matrix is array (0 to 2) of bit_vector(7 downto 0);

    > You would have greater flexability here if the dimension (0 to 2)
    > were unconstrained (like you did below)
    >
    > >
    > > function CPosition (x, y: bit_vector(7 downto 0)) return matrix;
    > >
    > > end ITRON_VFD;
    > >
    > > package body ITRON_VFD is
    > >
    > > function CPosition (x, y: bit_vector(7 downto 0))
    > > return matrix is variable result: matrix;
    > >
    > > constant sc: bit_vector(7 downto 0) := X"10";
    > > type matrix is array (NATURAL range <>) of bit_vector(7 downto 0);

    > This does not need to be here. Remove it. See note
    > above, you may want this as your declaration above.
    >
    > >
    > > begin
    > >
    > > result:=(sc, x, y);
    > >
    > > return result;
    > > end CPosition;
    > >
    > > end ITRON_VFD;
    > >
    > > --Code
    > > library IEEE;
    > > use IEEE.std_logic_1164.all;
    > > use WORK.ITRON_VFD.all;
    > >
    > > entity test is
    > > port(clk, rst : in std_logic;
    > > outp : out bit_vector(7 downto 0));
    > > end test;
    > >
    > > architecture rtl of test is
    > > type abc is array (0 to 2) of bit_vector(7 downto 0);

    >
    > Type abc is not the same as matrix.
    > You can remove this declaration.
    >
    > > signal ram: abc;

    > You must use type matrix here.
    >
    > > subtype int_r is integer range 0 to abc'HIGH+1;

    > If you delete abc above, you might wish to use matrix here.
    >
    > > signal n: int_r;
    > > begin
    > >
    > > ram<=CPosition(X"23", X"44");
    > >
    > > process(clk, rst, n, ram)
    > > begin
    > > if rising_edge(clk) then
    > > if rst='0' or n=abc'HIGH+1 then
    > > outp<=X"00";
    > > n<=0;
    > > elsif n<abc'HIGH+1 then
    > > outp<=ram(n);
    > > n<=n+1;
    > > end if;
    > > end if;
    > > end process;
    > >
    > > end rtl;
    > >
    > > This is my first project using function calls from my own package and as

    far
    > > as i can see there isnt any type conflict between the two, the function
    > > expects two bit vectors of length 8 and returns an array of bit vectors.
    > > Any clues.
    > >
    > > Thanks,
    > > Matt
    > >
    > >

    >
     
    Matt North, Oct 24, 2003
    #3
  4. On Fri, 24 Oct 2003 08:36:01 +0100, "Matt North"
    <m.r.w.north@NO_SPAMrl.ac.uk> wrote:

    >Jim,
    >
    >I thought that because both abc, and matrix had the same physical size
    >(array of 3 bytes of type bit_vector)
    >that it wouldnt differentiate between the two


    VHDL is strongly typed, and it makes a distinction between things that
    (to you) seem the same.

    Further, if you have two *identical* definitions for a type (in
    different packages) they define different types even if the types have
    the same unqualified name.

    This is done so that operator overloading works correctly.
    (Presumably there are other reasons, but that seems to be the most
    important one to me.)

    Regards,
    Allan.
     
    Allan Herriman, Oct 24, 2003
    #4
  5. Matt North

    Jim Lewis Guest

    Matt,
    Read Allan's repsonse first.

    You can get some flexability by defining matrix as:
    type matrix is array (NATURAL range <>) of bit_vector(7 downto 0);

    Then when you create a signal you bound it just
    like std_logic_vector:

    signal Ram : matrix(0 to 2) ;

    What it seems you need is an unconstrained array of
    unconstrained arrays. Unfortunately we don't have that
    yet.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    Matt North wrote:
    > Jim,
    >
    > I thought that because both abc, and matrix had the same physical size
    > (array of 3 bytes of type bit_vector)
    > that it wouldnt differentiate between the two
    > This may cause problems as i hope to have many functions in a package which
    > all o/p arrays of varying lengths (all of type bit_vector)
    > which will be i/p into one big array in the entity!
    >
    > Thanks for your help,
    > Matt
    >



    >>Matt North wrote:
    >>
    >>>Ive got a package called ITRON_VFD which holds a function called

    >
    > CPosition,
    >
    >>>Both the package and code calling the function are shown below,
    >>>compiling in Leonardo gives the following error -- pkg_test.vhd",line

    >
    > 17:
    >
    >>>Error, no feasible entries for subprogram CPosition.
    >>>compiling in Modelsim gives the following error --pkg_test.vhd(18): type
    >>>error resolving function call: cposition
    >>>
    >>>--Package
    >>>library ieee;
    >>>use ieee.std_logic_1164.all;
    >>>use ieee.numeric_std.all;
    >>>
    >>>package ITRON_VFD is
    >>>
    >>>type matrix is array (0 to 2) of bit_vector(7 downto 0);

    >>
    >>You would have greater flexability here if the dimension (0 to 2)
    >>were unconstrained (like you did below)
    >>
    >>
    >>>function CPosition (x, y: bit_vector(7 downto 0)) return matrix;
    >>>
    >>>end ITRON_VFD;
    >>>
    >>>package body ITRON_VFD is
    >>>
    >>>function CPosition (x, y: bit_vector(7 downto 0))
    >>> return matrix is variable result: matrix;
    >>>
    >>>constant sc: bit_vector(7 downto 0) := X"10";
    >>>type matrix is array (NATURAL range <>) of bit_vector(7 downto 0);

    >>
    >>This does not need to be here. Remove it. See note
    >>above, you may want this as your declaration above.
    >>
    >>
    >>>begin
    >>>
    >>>result:=(sc, x, y);
    >>>
    >>>return result;
    >>>end CPosition;
    >>>
    >>>end ITRON_VFD;
    >>>
    >>>--Code
    >>>library IEEE;
    >>>use IEEE.std_logic_1164.all;
    >>>use WORK.ITRON_VFD.all;
    >>>
    >>>entity test is
    >>> port(clk, rst : in std_logic;
    >>> outp : out bit_vector(7 downto 0));
    >>>end test;
    >>>
    >>>architecture rtl of test is
    >>>type abc is array (0 to 2) of bit_vector(7 downto 0);

    >>
    >>Type abc is not the same as matrix.
    >>You can remove this declaration.
    >>
    >>
    >>>signal ram: abc;

    >>
    >>You must use type matrix here.
    >>
    >>
    >>>subtype int_r is integer range 0 to abc'HIGH+1;

    >>
    >>If you delete abc above, you might wish to use matrix here.
    >>
    >>
    >>>signal n: int_r;
    >>>begin
    >>>
    >>>ram<=CPosition(X"23", X"44");
    >>>
    >>>process(clk, rst, n, ram)
    >>>begin
    >>> if rising_edge(clk) then
    >>> if rst='0' or n=abc'HIGH+1 then
    >>> outp<=X"00";
    >>> n<=0;
    >>> elsif n<abc'HIGH+1 then
    >>> outp<=ram(n);
    >>> n<=n+1;
    >>> end if;
    >>> end if;
    >>>end process;
    >>>
    >>>end rtl;
    >>>
    >>>This is my first project using function calls from my own package and as

    >
    > far
    >
    >>>as i can see there isnt any type conflict between the two, the function
    >>>expects two bit vectors of length 8 and returns an array of bit vectors.
    >>>Any clues.
    >>>
    >>>Thanks,
    >>>Matt
    >>>
    >>>

    >>

    >
    >
     
    Jim Lewis, Oct 25, 2003
    #5
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