Function for direct conversion integer > slv

Discussion in 'VHDL' started by aleksazr@gmail.com, Dec 24, 2012.

  1. Guest

    (using ieee.numeric_std.all)

    A BRAM has two input signals (that I'm interested in)
    WEA and ADDRA, both are slv.

    I'm connecting std_logic to WEA, and integer to ADDRA.

    Of course, tools complain, so I use the following function
    (for WEA) to convert std_logic to std_logic_vector(0 downto 0):

    function vectorize(s: std_logic) return std_logic_vector is
    variable v: std_logic_vector(0 downto 0);
    begin

    v(0) := s;
    return v;
    end;

    so I can type
    wea => vectorize(sl)
    directly into the port map.

    ADDRA requires two steps:
    convert integer to unsigned, then unsigned to slv:
    ADDRA => slv(to_unsigned(int, width))

    but ISE doesn't accept that directly in the port map,
    and I have to create another signal just for that.

    Is it possible to write a function similar to vectorize
    that will accept an integer and convert it into slv,
    so I can write something like
    ADDRA => to_slv(to_unsigned(int, width))
    or am I stuck at creating another signal?
    , Dec 24, 2012
    #1
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  2. KJ Guest

    On Monday, December 24, 2012 6:54:32 AM UTC-5, wrote:
    > (using ieee.numeric_std.all) A BRAM has two input signals (that I'm
    > interested in) WEA and ADDRA, both are slv. I'm connecting std_logic
    > to WEA, and integer to ADDRA. Of course, tools complain, so I use the
    > following function (for WEA) to convert std_logic to
    > std_logic_vector(0 downto 0):
    >
    > function vectorize(s: std_logic) return std_logic_vector is variable
    > v: std_logic_vector(0 downto 0);
    > begin
    > v(0) := s;
    > return v;
    > end;
    >
    > so I can type wea => vectorize(sl) directly into the port map.


    You can also connect the port map like this and avoid the function
    wea(0) => sl

    > ADDRA requires two steps: convert integer to unsigned, then unsigned
    > to slv: ADDRA => slv(to_unsigned(int, width)) but ISE doesn't accept
    > that directly in the port map, and I have to create another signal
    > just for that. Is it possible to write a function similar to vectorize
    > that will accept an integer and convert it into slv, so I can write
    > something like ADDRA => to_slv(to_unsigned(int, width)) or am I stuck
    > at creating another signal?


    No, you won't be able to create a function to put into the port map. VHDL
    does allow you to put type conversion functions in the port map but the
    conversion from integer to slv (or even just to unsigned) doesn't meet
    the VHDL definition of a conversion function that is allowable in a port
    map.

    Another option which is useful if you will be using these BRAMs a lot and
    don't like the drudgery of creating a new signal every time you go to use
    it is to create a new entity that wraps the BRAM with a more friendly
    interface. That new entity can allow ADDRA to be an integer allowing for
    easy hookup. Inside the architecture do the conversion.

    Kevin Jennings
    KJ, Dec 24, 2012
    #2
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  3. Guest

    Ok, thank you
    , Dec 25, 2012
    #3
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