functional verification

[Aji]

Hi all,

I will be in charge of implementing algorithms on FPGA (signal processing).
Some people in the team are used to write the algorithms from scratch in
vhdl. They don't build or use (even if it already exists) C model to check
the functionality of the core and pretends : "Anyway, if it doesn't work, we
will see it".

I am a beginner in programming in VHDL, but from what I have seen in my
first previous experience, people always used C models before developping in
VHDL. So I am wondering if there exist a common practice, or if it depends
on algorithms that are implemented. I still thinks it's time saving using
the C model and doing block by block bit true tests, especially if the
stuff doesn't work. What do you do ?

Aji.

 

[Zara]

Hi all,

I will be in charge of implementing algorithms on FPGA (signal processing).
Some people in the team are used to write the algorithms from scratch in
vhdl. They don't build or use (even if it already exists) C model to check
the functionality of the core and pretends : "Anyway, if it doesn't work, we
will see it".

I am a beginner in programming in VHDL, but from what I have seen in my
first previous experience, people always used C models before developping in
VHDL. So I am wondering if there exist a common practice, or if it depends
on algorithms that are implemented. I still thinks it's time saving using
the C model and doing block by block bit true tests, especially if the
stuff doesn't work. What do you do ?

Aji.

Program directly in VHDL and make test in VHDL

Zara

 

[Mike Treseler]

I am a beginner in programming in VHDL, but from what I have seen in my
first previous experience, people always used C models before developping in
VHDL. So I am wondering if there exist a common practice, or if it depends
on algorithms that are implemented. I still thinks it's time saving using
the C model and doing block by block bit true tests, especially if the
stuff doesn't work. What do you do ?

Where I work, matlab is popular for defining dsp algorithms.
Once the algorithm is defined, vhdl simulation and synthesis
is straightforward. New products like this:

http://www.mathworks.com/products/filterhdl/index.html?fp

claim to do the vhdl code for you in some cases.

-- Mike Treseler