Galois Multiplier

Discussion in 'VHDL' started by Patrick, Feb 11, 2005.

  1. Patrick

    Patrick Guest

    Hello,

    I'm currently designing à Reed-Solomon decoder and I need to implement
    a Galois multiplier optimized for area..

    Now it takes 50 Logic Elements on Cyclone Altera and for the
    Berlekamp-Massey alogorithm I need 6 t + 2 multiplier (t=16) so I need
    4900 Logic Elements only for the multiplier !!!

    Do you know if there is a good paper for optimized area on altera
    target ?

    My VHDL model have 64 AND and a few XOR !!!

    Thanks for good ideas...
     
    Patrick, Feb 11, 2005
    #1
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  2. Patrick

    Jezwold Guest

    google might be a good place to start.
     
    Jezwold, Feb 11, 2005
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  3. Patrick wrote:
    > My VHDL model have 64 AND and a few XOR !!!


    How big (# bits) are your Galois elements?

    Regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Feb 11, 2005
    #3
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