Gary's comment on languages

Discussion in 'VHDL' started by HT-Lab, Oct 31, 2011.

  1. HT-Lab

    HT-Lab Guest

    Hi All,

    I found the statement below (VHDL is better than Verilog) from Gary
    Smith quite refreshing (if that is the right word) if you consider he
    operates in the same "world" as Aart De Geus (CEO Synopsys) who said
    that VHDL is dead and perhaps more infamously Joe Costello (ex CEO
    Cadence) who said that VHDL was a $400 million dollar mistake.

    Gary replied to a John Cooley question on C/C++/SystemC Synthesis:

    http://www.deepchip.com/items/0494-02.html

    Hans
    www.ht-lab.com

    PS I am not trying to start a language war, we all know that both
    Verilog and VHDL are great RTL languages.


    From: Gary Smith <gary=user domain=garysmitheda got calm>

    Hi, John,

    A little history for those that aren't into language development. VHDL
    is a superior RTL language over Verilog. FORTRAN and Ada are superior
    parallel languages over C and the multiple C variants. The point is
    that unless there is a major revolt among Embedded Programmers we are
    stuck with C and SystemC. Catapult C, coming from the C side, and
    Forte, coming from the SystemC side, have done the best job of meeting
    design engineers demands based on inferior languages. Just as Design
    Compiler did for the RTL engineers.

    We've done a lot of ESL based tape outs over the last eight years.
    Saying that Catapult C is a failure is like saying Design Compiler was a
    failure in 1994. It ain't perfect but it's the best we've got; and it's
    improving every year.

    Don't blame the tools, blame the language.

    - Gary Smith
    Gary Smith EDA Santa Clara, CA
     
    HT-Lab, Oct 31, 2011
    #1
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