Gate Count and Power...

[john.deepu]

Hi all,
Can anyone tell me what will be the approximate power consumpton of
a 95K block in TSMC 13u Process. I know the exact power will be
depending on the switching activity in the nets. But I am looking for
an approximate value..

My 94K block is consuming 77mW of power (reported by power compiler)..
Do you think its huge??

regards
DEEPU C JOHN

 

[glen herrmannsfeldt]

Can anyone tell me what will be the approximate power consumpton of
a 95K block in TSMC 13u Process. I know the exact power will be
depending on the switching activity in the nets. But I am looking for
an approximate value..

My 94K block is consuming 77mW of power (reported by power compiler)..
Do you think its huge??

What is the approximate clock frequency? Without that, any power
estimate could be off by about 10 orders of magnitude.

-- glen

 

[mk]

Hi all,
Can anyone tell me what will be the approximate power consumpton of
a 95K block in TSMC 13u Process. I know the exact power will be
depending on the switching activity in the nets. But I am looking for
an approximate value..

My 94K block is consuming 77mW of power (reported by power compiler)..
Do you think its huge??

You can calculate a very approximate power consumption like this:
Take the power consumption of a nand2 (1x drive) cell (assuming your
94k number is in terms of this) and assume that the average load on
each nand2 is a certain pf load. Also assume a certain frequency of
change on inputs and outputs of the cells based on a certain
percentage of your clock frequency. Now you can use the following
equation to get a very rough approximation of power:
Pavg = (total energy of inputs) * A * F + C * Vdd^2* B * F (per cell)

where A is the percentage of input changes and B is percentage of
output changes and F is your clock frequency.
Now if you assume energy of inputs is 0.03 uW/MHz, F=10MHz, A=.5,
B=0.5, C=0.05 and Vdd = 1.3 you get Pavg = .36125 uW per cell. With
94K cells this is 33.9 mW which shows that your 77mW is not
outrageously out of range assuming your actual numbers are anywhere
near the assumptions.

 

[john.deepu]

Hi all,
Thanks for the replies.. I forgot to mention my clock frequency its
around 132 MHz. It seems I used a wrong wireload model(tsmc13_wl10)
for reporting power with power compiler. When I used tsmc13_wl50(which
I used for synthesis).
The total power has been increased to around 160mW.
The PC report shows
Cell Internal power -38mW
Switching power -120 mW

I doubt whether to use a custom wireload model genrted by DC, or the
ones given by TSMC. can you giveme some suggestions??

thanks
Deepu John