gate level simulation

[jasperng]

hi there, i wanna do a gate level simulation on my design after synthesis using lenardo spectrum.

I generated .vhd and .sdf file from leonardo spectrum. Can some one guide me on how to do the simulation using modelsim se ? I tried to compile it but it seems that im missing some library as the modelsim doenst understand the instantation of the gate used in the netlist from leonardo spectrum....

Also, issit better to do gate level simulation in verilog format netlist instaed of VHDL format netlist ? ...

# vsim -sdftyp /tb_adder/UUT=C:/test_synthesis/adder/synthesis/half_adder.sdf work.tb_adder
# Loading C:\FPGAdv71LSPS\Modeltech\win32/../std.standard
# Loading C:\FPGAdv71LSPS\Modeltech\win32/../ieee.std_logic_1164(body)
# Loading C:\FPGAdv71LSPS\Modeltech\win32/../ieee.numeric_std(body)
# Loading work.tb_adder(behavior)
# Loading work.half_adder(behavioral)
# ** Warning: (vsim-3473) Component instance "ix1 : and02" is not bound.
# Time: 0 ns Iteration: 0 Region: /tb_adder/uut File: C:/adder simulation/half_adder_0.vhd
# ** Warning: (vsim-3473) Component instance "ix7 : aoi21" is not bound.
# Time: 0 ns Iteration: 0 Region: /tb_adder/uut File: C:/adder simulation/half_adder_0.vhd
# ** Warning: (vsim-3473) Component instance "ix104 : inv01" is not bound.
# Time: 0 ns Iteration: 0 Region: /tb_adder/uut File: C:/adder simulation/half_adder_0.vhd
# ** Warning: (vsim-3473) Component instance "ix106 : inv01" is not bound.
# Time: 0 ns Iteration: 0 Region: /tb_adder/uut File: C:/adder simulation/half_adder_0.vhd
# ** Error: (vsim-SDF-3250) C:/test_synthesis/adder/synthesis/half_adder.sdf(14): Failed to find INSTANCE '/tb_adder/uut/ix1'.
# ** Error: (vsim-SDF-3250) C:/test_synthesis/adder/synthesis/half_adder.sdf(23): Failed to find INSTANCE '/tb_adder/uut/ix7'.
# ** Error: (vsim-SDF-3250) C:/test_synthesis/adder/synthesis/half_adder.sdf(34): Failed to find INSTANCE '/tb_adder/uut/ix104'.
# ** Error: (vsim-SDF-3250) C:/test_synthesis/adder/synthesis/half_adder.sdf(41): Failed to find INSTANCE '/tb_adder/uut/ix106'.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "C:/test_synthesis/adder/synthesis/half_adder.sdf".
# Time: 0 ns Iteration: 0 Region: /tb_adder File: C:/adder simulation/tb_adder.vhd
# Error loading design

these are the error encountered ..

my vhdl netlist loooks like this

-- Definition of half_adder
--
-- 12/04/08 13:07:06
--
-- LeonardoSpectrum Level 3, 2005a.82
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity half_adder is
port (
a : IN std_logic ;
b : IN std_logic ;
sum : OUT std_logic ;
carry : OUT std_logic) ;
end half_adder ;

architecture Behavioral of half_adder is
signal carry_EXMPLR, nx103, nx105: std_logic ;

component and02
port (
A0,A1 : in std_logic;
Y : out std_logic);
end component;

component aoi21
port (
A0,A1,B0 : in std_logic;
Y : out std_logic);
end component;

component inv01
port (
A : in std_logic;
Y : out std_logic);
end component;


begin
carry <= carry_EXMPLR ;
ix1 : and02 port map ( Y=>carry_EXMPLR, A0=>b, A1=>a);
ix7 : aoi21 port map ( Y=>sum, A0=>nx103, A1=>nx105, B0=>carry_EXMPLR);
ix104 : inv01 port map ( Y=>nx103, A=>a);
ix106 : inv01 port map ( Y=>nx105, A=>b);
end Behavioral ;