gated clock

Discussion in 'VHDL' started by patrick.melet@dmradiocom.fr, Mar 21, 2007.

  1. Guest

    hi,

    I have a design with two clock that I want to mux toward a single
    clock like this

    with mode select CLK <=
    CLK_1 when mode_1,
    CLK_2 when mode_2,
    CLK_1 when others;

    Is there another manner to do this because Quartus says that CLK is a
    gated clock !

    thanks
     
    , Mar 21, 2007
    #1
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  2. wrote:

    > I have a design with two clock that I want to mux toward a single
    > clock like this
    >
    > with mode select CLK <=
    > CLK_1 when mode_1,
    > CLK_2 when mode_2,
    > CLK_1 when others;
    >
    > Is there another manner to do this because Quartus says that CLK is a
    > gated clock !


    http://groups.google.com/groups/search?q=fpga "gated clock"
     
    Mike Treseler, Mar 24, 2007
    #2
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