gated clock

P

patrick.melet

hi,

I have a design with two clock that I want to mux toward a single
clock like this

with mode select CLK <=
CLK_1 when mode_1,
CLK_2 when mode_2,
CLK_1 when others;

Is there another manner to do this because Quartus says that CLK is a
gated clock !

thanks
 

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