General question on access SRAM

Discussion in 'VHDL' started by picnanard, Jul 24, 2007.

  1. picnanard

    picnanard

    Joined:
    Mar 5, 2007
    Messages:
    19
    I want control the read and write (SRAM single data port) with FPGA I want stick a read cycle after write cycle. See below
    CS ----\_________________/------
    RD ----\_______/-----------------
    WR -------------\________/-----------

    According your experience
    Can I do that?
    The data sheet indicate the data still on the bus 8ns after the RD raising edge.
     
    Last edited: Jul 24, 2007
    picnanard, Jul 24, 2007
    #1
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